I'm working on a PC board design that will have a Xilinx FX12 FPGA on
its mainboard. I want to run the IDE over to my FPGA so that my FPGA
has access to the hard drive. Generally a PC consists of a IDE
"Controller" ATA style which is located on any generic IDE hard drive
and an IDE "Host Interface" which is what you'll find on the mother
board's south bridge or Super I/O chip. What I want to do is
essentially add a second "IDE Host Interface" into my FPGA allowing it
access to the same hard drive as the rest of the PC uses. Since I
haven't designed IDE host interfaces before, I want to find out this
feasibility and possibly this idea and a timing diagram of a typical
hard drive access sequence. Would I need to daisy chain the interface
through the FPGA? Or could they simply be parrallel? Parrallel would
require open drain outputs on signals like the chip selects, interrupt
requests, etc in order to keep the two host interfaces (one in my FPGA
and the second out on the motherboard) from stepping on each other.
However, I haven't been able to locate this information. Has anyone
done this before?

Pappy

slewis at bdatech.com wrote:

This information is available in the ATA specification.

Would I need to daisy chain the
I can't comment on the electrical aspects of this, but I can assure you from a system standpoint, you're asking for trouble. This is a sure way to corrupt data on your harddisk, that's for sure! I must admit I can't even think of why you'd want/need to do this??? If you need to grant access to the PC harddisk data to a peripheral via an FPGA, I would've thought you'd implement a communications channel over PCI and have a driver request data via the OS?!? If you are really hell-bent on doing it this way, then I'd suggest you connect the drive solely via the FPGA and have your PC access the data that way. Your system problems in regards to sharing a drive still remain, but your electrical ones go away. Regards, -- Mark McDougall, Software Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266

slewis at bdatech.com wrote: After thinking about it for a few more minutes, I've realised that you definitely can't run them in parallel. You have two hosts connected on the same ATA bus, and no way of arbitrating between them. So regardless of what you do in the FPGA, your PC controller will trounce all over your FPGA controller when it's talking to the device. Would you *could* do I suppose is to sit the FPGA between your PC host controller and the device. Then it could 'emulate' a device as far as the PC sees it, and allow the FPGA to control access to the real device. However, this would play havoc with your performance and all sorts of software timeouts in your PC OS drivers. In short, it's not something I would consider doing myself. What is your exact problem/requirement? I'm betting there's a better way to do it!?! Regards, -- Mark McDougall, Software Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266