Hello everybody,

I was using the opb2wb core in my Xilinx project to connect an
wb_uart16550 to the micoblaze.
I have some problems to integrate this core in my projects.
I am new in the development of microblaze achitecture then I don't
know if I do it allright.
OK then:

I have downloaded the OPB2WB file and unziped it in
../EDK/HW/C:\EDK\hw\XilinxProcessorIPLib\pcores directory.
Then I included the opb2wb peripheral in my micoblaze project, and set
it correctly (I think !!!!)
I also tryed to create the netlist but it was an missmatch error
between the mpd file and the .v file : one time the rst signal is
named "rst" and in the other "opb_rst". Why??? It is realy an error?????
I look in the netlist file and the name is "rst".

if I change in the mpd file "opb_rst" to "rst" the netlist succed and
is created.

Then when I integrate my micoblaze project in my Xilinx VHDL project
and I do a synthesis it will work but when I wanted to translate it I
have an error:

ERROR:NgdBuild:604 - logical block
'Inst_micro_blaze/opb2wb_rs422/opb2wb_rs422'
with type 'opb2wb' could not be resolved. A pin name misspelling
can cause
this, a missing edif or ngc file, or the misspelling of a type
name. Symbol
'opb2wb' is not supported in target 'spartan3'.

I dont know why I have this error. the option STYLE in mpd file is set
to MIX then (normaly) it knows where to find the netlist file!!!


If somebody understand what my problem is ... thank you for your help.

Hello,
| I have downloaded the OPB2WB file and unziped it in
| ../EDK/HW/C:\EDK\hw\XilinxProcessorIPLib\pcores directory.
| Then I included the opb2wb peripheral in my micoblaze
| project, and set it correctly (I think !!!!) I also tryed to
| create the netlist but it was an missmatch error between the
| mpd file and the .v file : one time the rst signal is
| named "rst" and in the other "opb_rst". Why??? It is realy
| an error?????

Yes.

| I look in the netlist file and the name is "rst".

If the EDK is complaining about the signal, then you installed the core
correctly. What you are seeing is a bug that I found in '04? You can go
through and make the name the same in all places and it will work fine. I
sent a fix to Rudolf but apparently he never checked it in. Oh well.

| if I change in the mpd file "opb_rst" to "rst" the netlist
| succed and is created.
|
| Then when I integrate my micoblaze project in my Xilinx VHDL
| project and I do a synthesis it will work but when I wanted
| to translate it I have an error:
|
| ERROR:NgdBuild:604 - logical block
| 'Inst_micro_blaze/opb2wb_rs422/opb2wb_rs422'
| with type 'opb2wb' could not be resolved. A pin name
| misspelling can cause
| this, a missing edif or ngc file, or the misspelling of a
| type name. Symbol
| 'opb2wb' is not supported in target 'spartan3'.

Does the MPD contain a line like
OPTION ARCH_SUPPORT =
spartan2:spartan2e:spartan3:virtex:virtex2:virtex2p:virtexe

I believe I had to add this as well.

./ks

Hello, Valid with EDK 7.1: Some of these clues are taken from the FPGA mailing list 0- I´ve changed the data and address vectors of my WB core to adapt it to the 32 buses of the wrapper 1- Download the wrapper from opencores 2 - Copy the wrapper files to pcores directory 3- Change the bbd file to ################################################################################ ## ## Copyright (C) 2000-2004 ASICS World Services, LTD. ## www.asics.ws ## info at asics.ws ## ## Author: Rudolf Usselmann ## rudi at asics.ws ## ################################################################################ FILES ################################################################################ opb2wb.edn 3- Rename the .edn to opb2wb.edn 4- Change PORT opb_rst to PORT rst in the .mpd file PORT opb_rst = OPB_Rst, DIR = IN, BUS = SOPB PORT rst = OPB_Rst, DIR = IN, BUS = SOPB 5- Make the rst signal visible in the EDK to check if it is connected to the right reset global signal of your design 6- Edit the edif file to change (program "Xilinx ngc2edif" (version "G.31a")) to (program "none") (As Rudi explains in one of his email, Xilinx documentation about generating exportable netlists is not very clear) 7- Select address 8000 0000 for the wrapper Regards, Armando At 11:51 20/01/2006 -0500, you wrote: ---------------------------------------------------------------------------------------------------------------------- Armando Astarloa Cuéllar - Universidad del Pais Vasco UPV/EHU Tecnología Electrónica Departamento de Electrónica y Telecomunicaciones Escuela Superior de Ingenieros - Email: jtpascua at bi.ehu.es Ald. de Urquijo s/n Tel.: 34 - 94 - 601 73 04 48013 BILBAO (SPAIN) Fax.: 34 - 94 - 601 42 59 URL : http://det.bi.ehu.es/~apert ---------------------------------------------------------------------------------------------------------------------- -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20060123/c30baac1/attachment.htm