No it was not a joke. That is the going rate for the work that you required
doing.

A lot of people post here looking for someone else to do a job for them for
free thinking it is easy. VHDL/Verilog design is not easy as you will find
if you give it a go.

You will get help with problems here once you have made attempts yourself
but don't expect a free ride.



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You still dont get it do you ----- Original Message ----- From: shikhanshu at gmail.com> To: cores at opencores.org> Sent: Monday, February 13, 2006 12:28 PM Subject: [oc] to stuart...

hey stuart...

is that $150,000 thingy a joke???

btw...if u can really help me out with the subject it will be cool

No joke. US$15,000.00 would indeed make me serious about helping you
with your homework. But you need to pay me first in order to get any
help.

Waiting expectantly for your cashier's check,

Stuart

Another idea how to get this cheaper: Take the code that is available, rename the signals, remove some advanced functions, add a few bugs (it is not expected that it should be bug free) and you're done Martin ----- Original Message ----- From: "Stuart Brorson" sdb at cloud9.net> To: cores at opencores.org> Sent: Monday, February 13, 2006 2:16 PM Subject: Re: [oc] to stuart...