Mr.Rudolf Usselmann:
I have been worked as a hardware design engineer for almost 5 years . I have some questions in designing ICs. Would you please give me some advice .My design has a PLL , I have no experence in dealing with it .someone says , PLL has unstable time . I don't know how to do with it . Please tell me how to do and why . And more , can you give me some suggestion on improving design skills.
Can you recommanded some good book .

In general, if you don't understand how a PLL works, you're probably dealing with it from a digital designer's perspective. For that, it is simplest to view a PLL as a black box that outputs a clock with a frequency that is a multiple of its input clock frequency. PLLs use an error-feedback circuit to figure out when their output clock is at the correct frequency, and this circuit takes some time to converge. After convergence, the PLL said to be "locked" to its input frequency. Most PLLs will have a "lock" or "ready" signal coming out of them, and are also spec'ed to have a maximum unstable time before they achieve lock. Because some PLL designs can drift in and out of lock, the safest technique is to use a two-phase reset, where the first phase releases the PLL from reset, and starts an internal timer. When the timer expires, the second reset signal is released, which releases core logic from reset. Wikipedia has an extensive article on the subject: http://en.wikipedia.org/wiki/PLL - Guy -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20060303/79cb005b/attachment.htm