Hello , Had a question on the DDR SDRAM controller The 'dqs_q' port of the controller is 'out' only , so how does the controller perform read operations as the DQS ( or data strobe ) is genrated by the DDR SDRAM device for reads and for writes the memory controller generates the DQS The DQS port should be 'inout' ( 'in' for reads and 'out' for writes ) or maybe I'm missing something. If any user or the Author himself can answer , I'll appriciate. Best Regards Shehryar -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20060227/36b14852/attachment.htm

Hi Shehryar, I suppose that you are refering to the http://www.opencores.org/projects.cgi/web/ddr_sdr/overview core. I only looked at the key features on that page and it indeed mentions unidirectional DQS support (write only). This is NOT uncommon for FPGA DDR interfaces, though I also find this a pitty. The truth is.....the read for a DDR interface and using the DQS is really the pain of making a decent DDR interface. It is also possible to perform reads without using the DQS by simply using the relation between the CK, /CK and the read data. The FPGA clocks in the data often by using a phase shifted version of the CK,/CK clock. So it can work, but closing the timing requirements (including the PCB trace length requirements) is more difficult and therefore often slower. Best regards, Ralph ----- Original Message ----- From: Shehryar Shaheenshehryar.shaheen at u...> To: Date: Sun Feb 26 14:26:03 CET 2006 Subject: [oc] DDR SDRAM Question

On 2/26/06, Shehryar Shaheen shehryar.shaheen at ul.ie> wrote: Just a guess, but cores developed for ASIC use typically have a port triplet (in/out/enable) for bidirectional ports, since tristate functionality is implemented in the pad ring. - Guy -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20060227/e31ecc40/attachment.htm

Actaully, that interface is only for Xilinx Virtex-2/V2 Pro FPGAs (it may work for Spartan3/3Es and Virtex-4s). It should have a tri-state layer, but I think that has to go in your highest design layer. I never got it to work (but that was over a year ago), so unfortunatly that's about the extent of what I know about it. Mike On 2/27/06, Guy Hutchison ghutchis at gmail.com> wrote:

in my mind,during the writing operation the dqs is provided by your controller ,but when the controller reads the data from the DDR SDRAM ,the dqs signal is generated from the DDR SDRAM.the dqs is inout pin.that is to say, the dqs is the clock of the dq.You can refer to the ddr sdram spec. ----- Original Message ----- From: Shehryar Shaheenshehryar.shaheen at u...> To: Date: Sun Feb 26 14:26:03 CET 2006 Subject: [oc] DDR SDRAM Question