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Fw: Configurable processors gird for battle
by Unknown on Mar 30, 2006 |
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----- Original Message -----
From: "Ovidiu Lupas" ovilup at m...>
To: "opencores.org" cores at o...>
"prof. dr. Tiponut Virgil" tiponut at e...>
Date: Sat, 18 Dec 1999 09:10:58 +0200
Subject: [oc] Fw: Configurable processors gird for battle
>
> Configurable processors gird for battle
> http://www.eet.com/story/OEG19991217S0069
>
> SAN FRANCISCO — The emerging configurable-processor
market is
> heating up. Earlier this week, Zilog Inc. bought Production
Languages
> Corp., a pioneer in the field of configurable processors. And
on
> Monday (Dec. 20), Hewlett-Packard Co. and STMicroelectronics
will
> provide additional details about their collaborative effort to
bring
> push-button processor solutions to embedded-system design.
> > Meanwhile, configurable-pro-cessor vendor Tensilica Inc. (Sunnyvale,
> Calif.) is expected to announce a major deal soon with a large
> corporation that is speculated to be either HP or STM. Tensilica
> declined this past week to comment on the pending deal.
> > The moves signal a quickening interest in forging new techniques that
> tackle both hardware and software design issues at high levels
of
> abstraction. To that end, Motorola Inc.'s Semiconductor
Products
> Sector has unveiled its semiconductor reuse standard (SRS) at
its Web
> site, aimed at simplifying system-on-chip (SoC) designs with
multiple
> blocks of logic.
> > While the approaches differ, the configurable processors, as well as
> Motorola's SoC design technology initiative, all hope to
streamline
> complex designs and shorten design cycles to just a few
months.
>
> Tom Starnes, in charge of DSP and microcontroller analysis at > Dataquest Inc. (San Jose, Calif.), said that while many engineers are
> attracted to the idea of developing a configurable processor,
> particularly one with unique instructions, that approach does not
> always match up with the need for corporate prudence. The
established
> "black box" MPU architectures from vendors like ARM, IBM and
Motorola
> have defined instruction sets, support from multiple tool
vendors and
> a body of commercial software linked to them.
> > "A company can always go out and find another software guy that is
> familiar with, say, the MIPS architecture," said Starnes. "But
if
> someone has created a design with a unique instruction set,
then it
> is up to that company to maintain its software over time. That
is a
> tremendous responsibility that a company must bear. The new
guy may
> not be able to learn all the quirks of the guy who created the
> original design five years earlier." > > Also, while companies such as Production Languages Corp. (PLC; Fort
> Worth, Texas) or Tensilica claim they can generate a
development tool
> set that matches the processor, the customer is limited to
that
> primary tool set. By contrast, anyone using an established
controller
> can choose from among several tool vendors and buy a tool set
tuned
> to that particular application, Starnes said.
> > Configurable processors "could be said to be on the verge of > something revolutionary. But there is a certain danger of creating a
> kind of garage-shop atmosphere, with just a few people
controlling
> the technology," said Starnes. "That is why Zilog's move to
buy PLC
> really makes a lot of sense for Zilog."
> > Zilog, which licensed PLC's technology last June, views acquiring the
> company as a way of putting a firm foundation under its
strategy to
> supply the embedded market with products based on soft cores.
Working
> in defense electronics throughout much of the 1990s,
Production
> Languages developed a proprietary description language called
THISL
> (temporal hierarchical instruction set language) that
generates soft
> cores and development tool sets. The software based on THISL
is named
> Toolsmith.
> > By generating "soft" processor cores with the appropriate set of
> peripherals and development tools, Zilog expects to be able to
> quickly roll products for cell phones, Internet appliances and other
> fast-moving markets where specifications can change quickly.
> > PLC president David Fritz, 40, will join Zilog as a vice president
> charged with developing new processing cores, with
communications as
> a primary focus. PLC's five principal engineers will form the
nucleus
> of a Zilog processor design center in the Dallas area.
> > Zilog said it will use the PLC technology throughout its customer
> base. Earlier this fall, Zilog announced its network processor
> initiative, Cartezian, which will use a 32-bit configurable processor
> from Tensilica as the central processor and PLC cores as the
"edge,"
> or interface, processors.
> > Fritz said Zilog became serious about an acquisition in October after
> PLC was able to use THISL to create a 16-bit, fixed-point DSP
core
> named Mosquito. Introduced at the fall DSP World show,
Mosquito can
> run as fast as 200 MHz and requires only 20,000 gates of
logic.
>
> Fritz said PLC engineers created the RISC-based Mosquito in six
> weeks. The software description was implemented in an FPGA
that
> booted up successfully the first time. The core was tested on
an
> oscilloscope that "ran in lockstep with the simulation on the
show
> floor at DSP World," he said.
> > "If Zilog is going to offer voice-over-Internet Protocol, a fairly
> high-end DSP is required," Fritz said. "This will allow us to
match
> our silicon with the voice-over-IP opportunity."
> > Fritz estimated that the die size penalty of a soft core, compared
> with a custom-designed core, is "10 percent, going to 5
percent. But
> what this technology does is to raise the level of
abstraction, so
> that a designer can create an arbitrarily complex processor
that the
> designer could not fathom if he were limited to using VHDL or
Verilog
> descriptions."
> > For example, to create Mosquito, the PLC design team ran simulations
> that determined the DSP would be able to meet the performance
> requirements with a three-stage pipeline, rather than the five-stage
> pipeline originally planned. The THISL language considers a
pipeline
> as an abstract object, and redefining the pipeline logic took
only a
> few days of work, Fritz said.
> > Asked if the Dallas design group will move into the 32-bit space now
> targeted by Tensilica's Xtensa core, he said, "there is
nothing
> stopping us."
> > Fritz said his group has been charged by Zilog CEO Curtis Crawford
> with the task of creating five new processor cores within the
next 24
> months. The various product groups within Zilog could merge
the
> processor and DSP cores with Verilog descriptions of soft
> peripherals. > > Configurable VLIW designs > > Over the past two years, engineers from Hewlett-Packard and > STMicroelectronics have striven to bring to the embedded world the
> work that HP has done in developing VLIW-based concepts for
the IA-64
> platform with Intel Corp. HP scientist Joseph (Josh) Fisher,
an
> acknowledged expert in VLIW, said the two companies will
position
> their VLIW hardware and software development environment
between
> full-custom and off-the-shelf design approaches.
> > "Our technology provides the benefits of both. The driving vision is
> the ability to turn a crank, and out comes a targeted
architecture
> for performance-hungry applications," Fisher said.
> > Working with applications engineers from HP and STM, the customer
> would first select the best architecture for the application
—
> the HP/STM approach envisions a design described at the
> instruction-set architecture level. An HP tool would then spit out
> VLIW-oriented architectures based on the designers' input,
along with
> a tool set and specialized VLIW compiler that HP calls the
most
> advanced in the world.
> > The designer tweaks the design and recompiles to marry the processor
> to a specific application, Fisher said.
> > Loic Lietar, director of corporate strategic marketing for STM (San
> Diego), said, "There are real-world architecture-explorer
> capabilities that allow immediate feedback on the quality of the new
> design using a real tool chain."
> > Fisher said the first chip to tape out next year from the methodology
> is a digital still-image device to be used by HP. Silicon is
expected
> in the second half of 2000. In one of the important algorithms
keyed
> to the success of the device, the designer needed to devise a
> two-loop interchange in which the activity in one loop could interact
> with and affect the activity of the other, and vice versa. To
do so
> threw the balance of integer adders to integer multipliers out
of
> whack, Fisher said.
> > The designer needed to use 32 x 32-bit multipliers, but the tool
> suggested performance would be slowed. So the multipliers were
> rewritten as 16 x 32. Another engineer on the project suggested that
> would hurt performance even more, but that did not prove to be
the
> case, Fisher said. The instruction-level parallelism made up
for it.
>
> "Without the tool chain, he had no way of knowing this," Fisher said.
>
> Aside from the digital imager, neither Fisher nor Lietar would say
> what designs are being worked on. Since each design will
target a
> specific application, they declined to discuss speed or power
> consumption targets. > > "For a given application, we could build a much faster processor than
> you can get with a general-purpose CPU," Fisher added. "It's
very
> extensible."
> > Why evolve a new platform when so many flavors of architectures exist
> for embedded applications? Changing times, answered Lietar.
"Today's
> applications are, in effect, obsolete" for the designer
looking to a
> product launch in 12 or 18 months, he said. "Will you run
video on a
> cell phone? You might. Or maybe still digital images."
> > Perhaps the only applications for which the HP/STM approach might not
> be valid would be in straight control, where performance is
not a
> high priority or where there is not enough information up
front for
> the designer to properly customize his processor.
> > STM will take the technology and begin to sell SoC customers on the
> concept. Lietar dismissed suggestions that such a tool in
STM's
> arsenal would cannibalize existing embedded solutions.
> > "It's better to have two solutions to a problem than none," Lietar
> said. "We have SoC customers that are looking for extensible
> architectures." > > Tensilica's mum > > Meanwhile, Bernie Rosenthal, vice president of marketing at > Tensilica, declined to discuss the deal that's said to be pending
> between his company and HP, STM or some other large
corporation.
>
> "We've concentrated on making our technology easy to use, so that
> designers don't need to use internal pipelines and
> microarchitecture," he said. "They just need to describe it in a very
> general sense."
> > Rosenthal said the Zilog acquisition of PLC appeared designed to
> tackle the lower end of the market, slots where Zilog and PLC
have
> developed 8- and 16-bit architectures. "The space is heating
up but
> that's good for everybody," he said.
> > Over the next month, Tensilica plans to roll the second generation of
> its development platform, which features more extensible
processors.
>
> For more technology news, visit http://www.eet.com
>
>
------------------------------------------------------------------- -----
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> You can today at X.com - and we'll give you $20 to try it! Sign
> up today at X.com. It's quick, free, & there's no
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|||
|
Fw: Configurable processors gird for battle
by Unknown on Mar 30, 2006 |
Not available! | ||
|
----- Original Message -----
From: "Ovidiu Lupas" ovilup at m...>
To: "opencores.org" cores at o...>
"prof. dr. Tiponut Virgil" tiponut at e...>
Date: Sat, 18 Dec 1999 09:10:58 +0200
Subject: [oc] Fw: Configurable processors gird for battle
>
> Configurable processors gird for battle
> http://www.eet.com/story/OEG19991217S0069
>
> SAN FRANCISCO — The emerging configurable-processor
market is
> heating up. Earlier this week, Zilog Inc. bought Production
Languages
> Corp., a pioneer in the field of configurable processors. And
on
> Monday (Dec. 20), Hewlett-Packard Co. and STMicroelectronics
will
> provide additional details about their collaborative effort to
bring
> push-button processor solutions to embedded-system design.
> > Meanwhile, configurable-pro-cessor vendor Tensilica Inc. (Sunnyvale,
> Calif.) is expected to announce a major deal soon with a large
> corporation that is speculated to be either HP or STM. Tensilica
> declined this past week to comment on the pending deal.
> > The moves signal a quickening interest in forging new techniques that
> tackle both hardware and software design issues at high levels
of
> abstraction. To that end, Motorola Inc.'s Semiconductor
Products
> Sector has unveiled its semiconductor reuse standard (SRS) at
its Web
> site, aimed at simplifying system-on-chip (SoC) designs with
multiple
> blocks of logic.
> > While the approaches differ, the configurable processors, as well as
> Motorola's SoC design technology initiative, all hope to
streamline
> complex designs and shorten design cycles to just a few
months.
>
> Tom Starnes, in charge of DSP and microcontroller analysis at > Dataquest Inc. (San Jose, Calif.), said that while many engineers are
> attracted to the idea of developing a configurable processor,
> particularly one with unique instructions, that approach does not
> always match up with the need for corporate prudence. The
established
> "black box" MPU architectures from vendors like ARM, IBM and
Motorola
> have defined instruction sets, support from multiple tool
vendors and
> a body of commercial software linked to them.
> > "A company can always go out and find another software guy that is
> familiar with, say, the MIPS architecture," said Starnes. "But
if
> someone has created a design with a unique instruction set,
then it
> is up to that company to maintain its software over time. That
is a
> tremendous responsibility that a company must bear. The new
guy may
> not be able to learn all the quirks of the guy who created the
> original design five years earlier." > > Also, while companies such as Production Languages Corp. (PLC; Fort
> Worth, Texas) or Tensilica claim they can generate a
development tool
> set that matches the processor, the customer is limited to
that
> primary tool set. By contrast, anyone using an established
controller
> can choose from among several tool vendors and buy a tool set
tuned
> to that particular application, Starnes said.
> > Configurable processors "could be said to be on the verge of > something revolutionary. But there is a certain danger of creating a
> kind of garage-shop atmosphere, with just a few people
controlling
> the technology," said Starnes. "That is why Zilog's move to
buy PLC
> really makes a lot of sense for Zilog."
> > Zilog, which licensed PLC's technology last June, views acquiring the
> company as a way of putting a firm foundation under its
strategy to
> supply the embedded market with products based on soft cores.
Working
> in defense electronics throughout much of the 1990s,
Production
> Languages developed a proprietary description language called
THISL
> (temporal hierarchical instruction set language) that
generates soft
> cores and development tool sets. The software based on THISL
is named
> Toolsmith.
> > By generating "soft" processor cores with the appropriate set of
> peripherals and development tools, Zilog expects to be able to
> quickly roll products for cell phones, Internet appliances and other
> fast-moving markets where specifications can change quickly.
> > PLC president David Fritz, 40, will join Zilog as a vice president
> charged with developing new processing cores, with
communications as
> a primary focus. PLC's five principal engineers will form the
nucleus
> of a Zilog processor design center in the Dallas area.
> > Zilog said it will use the PLC technology throughout its customer
> base. Earlier this fall, Zilog announced its network processor
> initiative, Cartezian, which will use a 32-bit configurable processor
> from Tensilica as the central processor and PLC cores as the
"edge,"
> or interface, processors.
> > Fritz said Zilog became serious about an acquisition in October after
> PLC was able to use THISL to create a 16-bit, fixed-point DSP
core
> named Mosquito. Introduced at the fall DSP World show,
Mosquito can
> run as fast as 200 MHz and requires only 20,000 gates of
logic.
>
> Fritz said PLC engineers created the RISC-based Mosquito in six
> weeks. The software description was implemented in an FPGA
that
> booted up successfully the first time. The core was tested on
an
> oscilloscope that "ran in lockstep with the simulation on the
show
> floor at DSP World," he said.
> > "If Zilog is going to offer voice-over-Internet Protocol, a fairly
> high-end DSP is required," Fritz said. "This will allow us to
match
> our silicon with the voice-over-IP opportunity."
> > Fritz estimated that the die size penalty of a soft core, compared
> with a custom-designed core, is "10 percent, going to 5
percent. But
> what this technology does is to raise the level of
abstraction, so
> that a designer can create an arbitrarily complex processor
that the
> designer could not fathom if he were limited to using VHDL or
Verilog
> descriptions."
> > For example, to create Mosquito, the PLC design team ran simulations
> that determined the DSP would be able to meet the performance
> requirements with a three-stage pipeline, rather than the five-stage
> pipeline originally planned. The THISL language considers a
pipeline
> as an abstract object, and redefining the pipeline logic took
only a
> few days of work, Fritz said.
> > Asked if the Dallas design group will move into the 32-bit space now
> targeted by Tensilica's Xtensa core, he said, "there is
nothing
> stopping us."
> > Fritz said his group has been charged by Zilog CEO Curtis Crawford
> with the task of creating five new processor cores within the
next 24
> months. The various product groups within Zilog could merge
the
> processor and DSP cores with Verilog descriptions of soft
> peripherals. > > Configurable VLIW designs > > Over the past two years, engineers from Hewlett-Packard and > STMicroelectronics have striven to bring to the embedded world the
> work that HP has done in developing VLIW-based concepts for
the IA-64
> platform with Intel Corp. HP scientist Joseph (Josh) Fisher,
an
> acknowledged expert in VLIW, said the two companies will
position
> their VLIW hardware and software development environment
between
> full-custom and off-the-shelf design approaches.
> > "Our technology provides the benefits of both. The driving vision is
> the ability to turn a crank, and out comes a targeted
architecture
> for performance-hungry applications," Fisher said.
> > Working with applications engineers from HP and STM, the customer
> would first select the best architecture for the application
—
> the HP/STM approach envisions a design described at the
> instruction-set architecture level. An HP tool would then spit out
> VLIW-oriented architectures based on the designers' input,
along with
> a tool set and specialized VLIW compiler that HP calls the
most
> advanced in the world.
> > The designer tweaks the design and recompiles to marry the processor
> to a specific application, Fisher said.
> > Loic Lietar, director of corporate strategic marketing for STM (San
> Diego), said, "There are real-world architecture-explorer
> capabilities that allow immediate feedback on the quality of the new
> design using a real tool chain."
> > Fisher said the first chip to tape out next year from the methodology
> is a digital still-image device to be used by HP. Silicon is
expected
> in the second half of 2000. In one of the important algorithms
keyed
> to the success of the device, the designer needed to devise a
> two-loop interchange in which the activity in one loop could interact
> with and affect the activity of the other, and vice versa. To
do so
> threw the balance of integer adders to integer multipliers out
of
> whack, Fisher said.
> > The designer needed to use 32 x 32-bit multipliers, but the tool
> suggested performance would be slowed. So the multipliers were
> rewritten as 16 x 32. Another engineer on the project suggested that
> would hurt performance even more, but that did not prove to be
the
> case, Fisher said. The instruction-level parallelism made up
for it.
>
> "Without the tool chain, he had no way of knowing this," Fisher said.
>
> Aside from the digital imager, neither Fisher nor Lietar would say
> what designs are being worked on. Since each design will
target a
> specific application, they declined to discuss speed or power
> consumption targets. > > "For a given application, we could build a much faster processor than
> you can get with a general-purpose CPU," Fisher added. "It's
very
> extensible."
> > Why evolve a new platform when so many flavors of architectures exist
> for embedded applications? Changing times, answered Lietar.
"Today's
> applications are, in effect, obsolete" for the designer
looking to a
> product launch in 12 or 18 months, he said. "Will you run
video on a
> cell phone? You might. Or maybe still digital images."
> > Perhaps the only applications for which the HP/STM approach might not
> be valid would be in straight control, where performance is
not a
> high priority or where there is not enough information up
front for
> the designer to properly customize his processor.
> > STM will take the technology and begin to sell SoC customers on the
> concept. Lietar dismissed suggestions that such a tool in
STM's
> arsenal would cannibalize existing embedded solutions.
> > "It's better to have two solutions to a problem than none," Lietar
> said. "We have SoC customers that are looking for extensible
> architectures." > > Tensilica's mum > > Meanwhile, Bernie Rosenthal, vice president of marketing at > Tensilica, declined to discuss the deal that's said to be pending
> between his company and HP, STM or some other large
corporation.
>
> "We've concentrated on making our technology easy to use, so that
> designers don't need to use internal pipelines and
> microarchitecture," he said. "They just need to describe it in a very
> general sense."
> > Rosenthal said the Zilog acquisition of PLC appeared designed to
> tackle the lower end of the market, slots where Zilog and PLC
have
> developed 8- and 16-bit architectures. "The space is heating
up but
> that's good for everybody," he said.
> > Over the next month, Tensilica plans to roll the second generation of
> its development platform, which features more extensible
processors.
>
> For more technology news, visit http://www.eet.com
>
>
------------------------------------------------------------------- -----
> Want to send money instantly to anyone, anywhere, anytime?
> You can today at X.com - and we'll give you $20 to try it! Sign
> up today at X.com. It's quick, free, & there's no
obligation!
> http://click.egroups.com/1/332/0/_/3462/_/945498280
>
> -- Easily schedule meetings and events using the group
calendar! |
|||
1/1