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DDR SDRAM controller core
by Unknown on Mar 31, 2006 |
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Hallo everybody!
I just started with VHDL programming. I try to set up the DDR SDRAM core on a Altera StratixII FPGA by using QuartusII Software. Quartus has no UNISIM librarys and can't use the libs from Xilinx. But to compile the projekt, i'd ned them. unisim is used in reset and for the bufg. Has someone an idea how i can solve this Problem? best regards Stefan |
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DDR SDRAM controller core
by Unknown on Mar 31, 2006 |
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On Fri, 31 Mar 2006 07:56:42 +0000
"Stefan Zorn" s_zorn at hotmail.com> wrote:
SZ> Quartus has no UNISIM librarys and can't use the libs from Xilinx. But to
SZ> compile the projekt, i'd ned them. unisim is used in reset and for the bufg.
SZ> Has someone an idea how i can solve this
SZ> Problem?
You need to replace them with the similar Altera modules or modify the
code to get rid of them altogether. Depending on which signal requires
bufg it is possible that the synthesizer will assign it automatically
for you. Alternatively it can usually be done with attributes.
/Mikhail
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DDR SDRAM controller core
by Unknown on Mar 31, 2006 |
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I think that that core will only work in Xilinx Virtex-2 and Virtex-4
FPGAs, and possibly Spartan3/3Es. It uses a lot of Xilinx specific
primatives from what I rembember.
Mike
On 3/30/06, Stefan Zorn s_zorn at hotmail.com> wrote:
Hallo everybody!
I just started with VHDL programming.
I try to set up the DDR SDRAM core on a Altera StratixII FPGA by using
QuartusII Software.
Quartus has no UNISIM librarys and can't use the libs from Xilinx. But to
compile the projekt, i'd ned them. unisim is used in reset and for the bufg.
Has someone an idea how i can solve this
Problem?
best regards
Stefan
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