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SDRAM CORE by altera
by Unknown on Apr 10, 2006 |
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Hello Everybody! I try to set up the SDRAM CORE from Altera, wich is free with Quartus 5.1. For simulation the autogenerated test bench includes a memory model by altera. It gets, while initializing, start values from a file named sdram_0.dat. Sadly this file is empty. Does anybody know, how to wright such a file, or has one for me? Best Regards Stefan |
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SDRAM CORE by altera
by Unknown on Apr 10, 2006 |
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Hi Stefan,
you are not talking about the Altera SDRAM Controller Reference Design, are you? If so, just leave your hands from this. It does not implement all SDRAM commands, introduces large delays, does not support command nesting and so on... its just a reference design. Best regards, Joern Stefan Zorn schrieb:
Hello Everybody!
I try to set up the SDRAM CORE from Altera, wich is free with Quartus
5.1. For simulation the autogenerated test bench includes a memory
model by altera. It gets, while initializing, start values from a
file named sdram_0.dat. Sadly this file is empty. Does anybody know,
how to wright such a file, or has one for me?
Best Regards
Stefan
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http://www.opencores.org/mailman/listinfo/cores
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