hi,all i am a newbie to use opencores. now i want to build a wishbone bus.my tools is wb_builder.i can build a VHDL file,but i wish a verilog file.i change the file type to verilog,but make erroe. and all of entity in one file.so i cant compile the file.how can i do it. please help me! -- View this message in context: http://www.nabble.com/how-to-use-wb_builder-t1436945.html#a3878102 Sent from the OpenCores - IP Cores forum at Nabble.com. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20060412/89b94d41/attachment.htm