>
> Just tried with a simple design...well...usb1_core (o;
>
> Compiled out of the box with Altera Quartus but no chance
> with ISE6.1...some strange $PATH issues maybe...
>
>
> btw: downloading usb1_core and usb_phy resulted in an empty
> tar.gz file...web cvs checkout worked...
>
Solution seems simple (o;
Just use 'include "..\blah_blah.v"; to force it to use
current directory (o;
Now back to Xilinx ISE since Quartus got stuck with the core...
Synthesis completes now with tons of warnings...
Build fails as expected (o;
......
INFO:NgdBuild:526 - On the RAMB4_S8_S16 symbol
"ssvga_top_ssvga_fifo_ramb4_s8_1", the following properties are
undefined:
INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06,
INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B, INIT_0C, INIT_0D, INIT_0E,
INIT_0F. A
default value of all zeroes will be used.
ERROR:NgdBuild:466 - input pad net 'clk' has illegal connection.
Possible pins
causing this are:
pin C on block or1200_top_or1200_pm_sdf_2 with type FDCE,
pin C on block or1200_top_or1200_cpu_or1200_ctrl_ex_insn_18 with
type FDCE,
pin C on block or1200_top_or1200_tt_ttcr_29 with type FDCE,
pin C on block or1200_top_or1200_tt_ttcr_30 with type FDCE,
pin C on block or1200_top_or1200_tt_ttcr_26 with type FDCE,
pin C on block or1200_top_or1200_tt_ttcr_24 with type FDCE,
pin C on block or1200_top_or1200_tt_ttcr_25 with type FDCE,
pin C on block or1200_top_or1200_tt_ttcr_28 with type FDCE,
pin C on block or1200_top_or1200_tt_ttcr_23 with type FDCE,
pin C on block or1200_top_or1200_tt_ttcr_27 with type FDCE,
pin C on block or1200_top_or1200_tt_ttmr_31 with type FDCE,
pin C on block or1200_top_or1200_tt_ttmr_30 with type FDCE,
pin C on block or1200_top_or1200_tt_ttmr_29 with type FDCE,
pin C on block or1200_top_or1200_tt_ttmr_28 with type FDCE,
pin C on block or1200_top_or1200_tt_ttmr_27 with type FDCE,
pin C on block or1200_top_or1200_tt_ttmr_26 with type FDCE,
pin C on block or1200_top_or1200_tt_ttmr_25 with type FDCE,
pin C on block or1200_top_or1200_tt_ttmr_24 with type FDCE,
pin C on block or1200_top_or1200_tt_ttmr_23 with type FDCE,
pin C on block or1200_top_or1200_tt_ttmr_22 with type FDCE
Full reports at:
Synthesis: http://www.uclinux.net/xilinx/xsv_fpga_top.syr
Building: http://www.uclinux.net/xilinx/xsv_fpga_top.bld
Someone can put a light on it?
regards
rick
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