Dear all, Is any body used Or1k and can help me by answering to this questions: 1. Can you please advise how to arrange the code image? (How to arrange ram.ld file). 2. Is there a tool for conversion the build output into a file that can be loaded into the board? Is there a specific tool for conversion to Xilinx ram format? 3. In some code samples there is a reset.S file which implements reset starting from address 0x100 How does it suit the ram.ld declarations? 4. What is the sequence that causes the CPU to jump to first code instruction declared in ram.ld file? Regards, Avi Blanka __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20060614/dc3cd13a/attachment.htm

Avi Blanka wrote: Hi Avi This questions should be in the openrisc at opencores.org mailing list.

This depends on how you arranged SDRAM/SRAM/FLASH



You can use GDB to and JTAG software (JP1/JP2) to load program.



You have to tell the linker to put the first code ( _reset ) at address
0x100
This is done in the reset code

.section .vectors, "ax"
.org 0x100
_reset:
l.movhi r1,hi(_stack-4)
l.ori r1,r1,lo(_stack-4)
...



ram.ld is a set of instructions to the linker of how to link code and data.
After CPU reset, an exception is thrown and the PC is set to address
0x0000100 or 0xF000100 (depend on SR register)

Regards,
Nir