Dear All, I have a problem with OR1200 cores, I operated it in the board and trying to operate the UART , I hope you can help me to figure it out: 1. I connected ram size 4kx32 to WB0 slave and connected the uart to wb5 (slave and working with uart 32bit data size), When I operated the Uart, I saw that I have trampling over the command area, Is it a SW problem or is the problem in the ram.ld file? and how to solve this problem? 2. How can I know when it is a data cycle or when its fetch cycle? Is there some signal which indicate which kind of cycle it is? Best Regards, Avi.B --------------------------------- How low will we go? Check out Yahoo! MessengerÂ’s low PC-to-Phone call rates. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20060621/802e5317/attachment.htm