Hello, I was looking for a Memory Harness with Wishbone Slave interface written in Verilog. I've found the one written by Rudi time ago but it can only be initialized with random data. As far as you know, is there any Wishbone slave model that can be initialized with the content of an ASCII file? I've been looking a lot inside several OC projects but I could not find one suitable. Thanks in advance, Fabrizio -- ============================================ Fabrizio Fazzino - fabrizio at fazzino.it Fazzino.IT - http://www.fazzino.it ============================================