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Any one have ddr controller for MT46V32M16 -6
by Unknown on Jun 29, 2006 |
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hai any one have the ddr controller for MT46V32M16 -6. i am using this
for my v4MB board which have v4lx60 fpga. |
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Any one have ddr controller for MT46V32M16 -6
by Unknown on Jun 30, 2006 |
Not available! | ||
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Did you try the Xilinx Memory Interface Generator?
On 6/29/06, subin_cet at rediffmail.com subin_cet at rediffmail.com> wrote:
hai any one have the ddr controller for MT46V32M16 -6. i am using this
for my v4MB board which have v4lx60 fpga.
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http://www.opencores.org/mailman/listinfo/cores
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Any one have ddr controller for MT46V32M16 -6
by subin on Jul 1, 2006 |
subin
Posts: 1 Joined: Jul 4, 2006 Last seen: Nov 2, 2026 |
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Yes, But i think it's not supporting my board. That controller actually need two differential clocks and in my board there is only one. And also the pin assigmnent (showing error in the verify ucf tool). I tried it but it's not working in the hardware.i chose the chipscope to debug i all the inputs (dq and daddr) are showing zero even though i am driving it will vaid values from the testbench. and i am not getting anything from the ddr too(reading). The par simulation model is also not working. regards subin On Fri, 30 Jun 2006 Mike Delaney wrote :
Did you try the Xilinx Memory Interface Generator?
On 6/29/06, subin_cet at rediffmail.com subin_cet at rediffmail.com> wrote:
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hai any one have the ddr controller for MT46V32M16 -6. i am using this
for my v4MB board which have v4lx60 fpga.
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
_______________________________________________
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Any one have ddr controller for MT46V32M16 -6
by Unknown on Jul 1, 2006 |
Not available! | ||
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The differential clocks should be generated in the FPGA logic using DCMs to
get the phase differences, and I think either the DCMs will also give an
inverted output, or you can use an inverter for it. That said, I had the
same issue of the chip/package I was using was not supported by it, but it
that was 2 years ago. Check the Xilinx docs and support website. You
should be able to get it working.
Mike
On 1 Jul 2006 11:24:36 -0000, subin subin_cet at rediffmail.com> wrote:
Yes, But i think it's not supporting my board. That controller actually need two differential clocks and in my board there is only one. And also the pin assigmnent (showing error in the verify ucf tool). I tried it but it's not working in the hardware.i chose the chipscope to debug i all the inputs (dq and daddr) are showing zero even though i am driving it will vaid values from the testbench. and i am not getting anything from the ddr too(reading). The par simulation model is also not working. regards subin On Fri, 30 Jun 2006 Mike Delaney wrote :
>Did you try the Xilinx Memory Interface Generator?
>
>On 6/29/06, subin_cet at rediffmail.com subin_cet at rediffmail.com> wrote:
http://adworks.rediff.com/cgi-bin/AdWorks/sigclick.cgi/www.rediff.com/signature-home.htm/1507191490@Middle5?PARTNER=3>
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
>hai any one have the ddr controller for MT46V32M16 -6. i am using this
>for my v4MB board which have v4lx60 fpga.
>_______________________________________________
>http://www.opencores.org/mailman/listinfo/cores
>
>_______________________________________________
>http://www.opencores.org/mailman/listinfo/cores
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