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JOP Implementation in Spartan 3 - ISE 8.1i
by jardel on Aug 17, 2006 |
jardel
Posts: 8 Joined: May 31, 2008 Last seen: Dec 8, 2018 |
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Dear,
I'm experiencing some problems while implementing JOP (just
downloaded from CVS) in ISE 8.1i. The erro messages follow below:
Thanks in any advance.
Jardel.
---- error message ------
Process "Synthesize" completed successfully
Started : "Translate".
WARNING: en_US:en:en_EN is not supported as a language. Using usenglish.
Command Line: ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc jop.ucf -p
xc3s200-ft256-5 jop.ngc jop.ngd
Reading NGO file '/home/jardel/projetos/jop/jop/xilinx/s3sk/jop.ngc' ...
Applying constraints in "jop.ucf" to the design...
Checking timing specifications ...
Checking expanded design ...
ERROR:NgdBuild:604 - logical block 'cmp_core_cmp_stk_cmp_ram_cmp_xram_block'
with type 'xram_block' could not be resolved. A pin name misspelling can
cause this, a missing edif or ngc file, or the misspelling of a type
name.
Symbol 'xram_block' is not supported in target 'spartan3'.
ERROR:NgdBuild:604 - logical block 'cmp_core_cmp_bcf_cmp_jtbl' with type
'jtbl'
could not be resolved. A pin name misspelling can cause this, a
missing edif
or ngc file, or the misspelling of a type name. Symbol 'jtbl' is not
supported in target 'spartan3'.
ERROR:NgdBuild:604 - logical block 'cmp_core_cmp_fch_cmp_rom' with type
'rom'
could not be resolved. A pin name misspelling can cause this, a
missing edif
or ngc file, or the misspelling of a type name. Symbol 'rom' is not
supported
in target 'spartan3'.
ERROR:NgdBuild:604 - logical block 'cmp_core_cmp_fch_cmp_off' with type
'offtbl'
could not be resolved. A pin name misspelling can cause this, a
missing edif
or ngc file, or the misspelling of a type name. Symbol 'offtbl' is not
supported in target 'spartan3'.
NGDBUILD Design Results Summary:
Number of errors: 4
Number of warnings: 0
One or more errors were found during NGDBUILD. No NGD file will be written.
Writing NGDBUILD log file "jop.bld"...
Process "Translate" failed
---- end error message ------
Jardel Silveira
jardel at lesc.ufc.br
Federal Univerisity of Ceara
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JOP Implementation in Spartan 3 - ISE 8.1i
by Unknown on Aug 17, 2006 |
Not available! | ||
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Some VHDL files are generated by the microcode assembler.
See http://www.jopdesign.com/doc/build.pdf for further
details on the design flow.
Martin
----- Original Message -----
From: "jardel" jardel at lesc.ufc.br>
To: cores at opencores.org>
Sent: Thursday, August 17, 2006 8:39 PM
Subject: [oc] JOP Implementation in Spartan 3 - ISE 8.1i
_______________________________________________
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JOP Implementation in Spartan 3 - ISE 8.1i
by jardel on Aug 21, 2006 |
jardel
Posts: 8 Joined: May 31, 2008 Last seen: Dec 8, 2018 |
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Dear Mr. Schoeberl,
Thank you very much for your support. As i've read in your article, same address tables (in VHDL) are generated form jvm.asm. We've got running test app. Thanks. Jardel. Martin Schoeberl wrote:
Some VHDL files are generated by the microcode assembler.
See http://www.jopdesign.com/doc/build.pdf for further
details on the design flow.
Martin
----- Original Message ----- From: "jardel" jardel at lesc.ufc.br>
To: cores at opencores.org>
Sent: Thursday, August 17, 2006 8:39 PM
Subject: [oc] JOP Implementation in Spartan 3 - ISE 8.1i
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