Has anyone used the multimaster functionality of the I2C core? I have
a project that I inherited. The I2C bus worked running at 400kHz, and
now I need to upgrade it as I have another master on the bus (SBC).

I find that when the SBC attempts to access a slave (not the FPGA) on
the bus, the core will frequently hang (determined through o-scope and
Signal Tap) and I have to reboot my system.

System info: Altera Cyclone II, SW lang: AVHDL. I am developing my
SBC SW with an Aardvark device -> pretty handy tool itself as it reports
bus errors.

I have read the latest versions of the Core spec WISHBONE spec, and
I2C spec and see that the core is supposed to support I2C arbitration.
However, the core spec only has one brief (less than half a page)
statement on arbitration. The WISHBONE spec has its own arbitration
parameters and I don't know if these are conficting bits of info. I
haven't found much info on this topic on this site or anywhere else. I
realize that the processing at higher levels is user defined, but I need
some additional info or more articulated examples to go on.

Any help is appreciated. I am working on a project now that has a
timeline on it.

More info can be provided on my project.

Thanks
Steve