Hi everyone!
I'm searching any kind of information about AHB/Wishbone bridge. I
found in this forum some code, but (correct me if I'm wrong) it's not
finished.
I started writing this bridge but I'm newbie in writing such projects
in vhdl (never programmed Ip cores) and please You for help (most
important for me is connection between signals from AHB and Wishbone
and how conciliate incrementing burst from AHB with incrementing burst
from wishbone). Or if You have some code in vhdl or verilog i will be
very happy if You can share it to me :)

Best regards,
Martin