Hi,
I need a verilog code for 7_bit LFSR generating odd parity sequence.Kindly send
me the same.

Why can't you implement it yourself? This is a block that's about 100 gates in size. If it's the knowledge of how to do it that's lacking, then you need to spend more time searching the net. 2-3 google searches got me this link: http://www.xilinx.com/bvdocs/appnotes/xapp052.pdf Which has a table for maximal-length LFSR tap sequences from 3 to 168 bits. And it even tells you how to implement it. This is not a do-your-work-for-you mailing list. - Guy -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20060914/09ace5a9/attachment.htm