Hi, Has anyone here successfully used the SIR-only mode IrDA core? Because from what I'm seeing, it doesn't actually work!?! The testbench appears to work because the tx and rx ends are clocked by the same clock and also come out of reset at the same time. But in my simulation, the tx and rx ends are clocked asynchronously and also come out of reset at different times. The first few characters are transmitted and received correctly but then a 'bug' shows itself. The problem occurs in the irda_sir_decoder.v module when the counter transitions to 15 right in the middle of a zero pulse on the incoming stream. In this case 'zero' glitches and on the *next* wrap of the counter it's the wrong state to correctly decode a one. Has anyone else come across this??? Can the author comment? Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266

Mark McDougall wrote:

I've rewritten the decoder module and have gotten my simulation working. There's also potential problems introduced when dynamically switching the negation for TX/RX (at least after setting the baud rate), since clearing the FIFOs won't reset the receiver shift register. This could potentially be a problem on a real system when you need to negate RX in the core at startup - though thinking about it it should be safe if you set negation before setting the baud rate in the UART itself. Also, the documentation states that the MCR is R/W, when it is in fact write-only. Would still like to hear of others' experiences. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266