Hi, I doubt that it's MicroBlaze that is slow. If there is something that would be the bottleneck it's more likely the memory controller. MicroBlaze should be able to move this data much faster than 3.33 MHz. Are you using caches or is MicroBlaze also executing from the same external DDR memory? Göran Bilski -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of mencdaniele at tiscali.it Sent: 09 October 2006 13:02 To: cores at opencores.org Subject: [oc] Help with Microblaze Hello, I'm new in the forum. I have a S3E development board and I implemented a microblaze and a DDR with EDK 8.1 software; I use the MCH OPB DDR controller. I need to capture and store in the DDR a stream of 32 bit at 3,33MHz. I take the stream from a microblaze GPIO and I write the data in the DDR but when I reed the data stored I see that some data are missing; I use the OPB bus at 100MHz and also the DDR clock, I can't believe that microblaze is so slow so I think that I don't set correctly the cores or don't use the right C library. May sameone help me please? Thanks in advance Daniele _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Hello,

I'm new in the forum.
I have a S3E development board and I implemented a microblaze and a
DDR with EDK 8.1 software; I use the MCH OPB DDR controller.
I need to capture and store in the DDR a stream of 32 bit at 3,33MHz.
I take the stream from a microblaze GPIO and I write the data in the
DDR but when I reed the data stored I see that some data are missing; I
use the OPB bus at 100MHz and also the DDR clock, I can't believe that
microblaze is so slow so I think that I don't set correctly the cores or
don't use the right C library.
May sameone help me please?
Thanks in advance

Daniele

Hi, I use the dual port BRAM for store and execute the code; the DDR is only for the input data. In order to increase the speed I tried to use the mch opb ddr controller like xapp912 explain but the result don't change. I think that I writed a wrong (to slow) C code. The DDR in the S3E board is a Micron 32Mx16, in my code I use a 32bit data; when I write this single data in the memory I see (with the Oscilloscope) a double WE pulse signal and not one only so the controller make a double access to writa data and don't use a burst of 2 in order to do this. ----- Original Message ----- From: Goran Bilskigoran.bilski at x...> To: Date: Mon Oct 9 10:17:00 CEST 2006 Subject: [oc] Help with Microblaze

----- Original Message ----- From: Goran Bilskigoran.bilski at x...> To: Date: Mon Oct 9 10:17:00 CEST 2006 Subject: [oc] Help with Microblaze


Hi,

I use the dual port BRAM for store and execute the code; the DDR is
only for the input data.
In order to increase the speed I tried to use the mch opb ddr controller
like xapp912 explain but the result don't change.
I think that I writed a wrong (to slow) C code.
The DDR in the S3E board is a Micron 32Mx16, in my code I use a 32bit
data; when I write this single data in the memory I see (with the
Oscilloscope) a double WE pulse signal and not one only so the
controller make a double access to writa data and don't use a burst of 2
in order to do this.

Hi, You might want to try and combine writes to the DDR into 32Bytes at one go. Most DDR controllers work in burst 4 mode and with 64 bits data path this comes to 32 bytes. Also make sure that the addresses you use span the columns first and then banks and then rows. Last, make sure that DRAM controller can handle 4 open banks and that you run correct refresh cycles all of these can cause your performance to be reduced and cause data loss. Erez. ----- Original Message ---- From: "mencdaniele at tiscali.it" mencdaniele at tiscali.it> To: cores at opencores.org Sent: Tuesday, October 10, 2006 4:31:52 AM Subject: Re: [oc] Help with Microblaze Hi, I use the dual port BRAM for store and execute the code; the DDR is only for the input data. In order to increase the speed I tried to use the mch opb ddr controller like xapp912 explain but the result don't change. I think that I writed a wrong (to slow) C code. The DDR in the S3E board is a Micron 32Mx16, in my code I use a 32bit data; when I write this single data in the memory I see (with the Oscilloscope) a double WE pulse signal and not one only so the controller make a double access to writa data and don't use a burst of 2 in order to do this. ----- Original Message ----- From: Goran Bilskigoran.bilski at x...> To: Date: Mon Oct 9 10:17:00 CEST 2006 Subject: [oc] Help with Microblaze _______________________________________________ http://www.opencores.org/mailman/listinfo/cores -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20061010/3c9c08b9/attachment.htm

Hello, I use the mch_opb_ddr controller in the Xilinx edk, so I think (and hope) that the address is linked right. yestrday I saw that the time to capture a 32 bit from an I/O and write them in the DDR is 320 nsec; I have a 32Mx16 bit DDR and I see that when I take a 32bit from I/O and write the DDR I have two impulse in the WE pin like a duble 16 bit write access and not a single access with burst = 2. ----- Original Message ----- From: Erez Birenzwigerez_birenzwig at y...> To: Date: Mon Oct 9 21:32:59 CEST 2006 Subject: [oc] Help with Microblaze

Hi Daniele, The WE pin on SDRAM and DDR is not used only during write Op, you should sample both RAS/CAS/WE pins to know exactly which command is executing. WE pin is asserted both on PRECHARGE and WRITE command. If you want to have a chance to use burst access to the DDR try to enable the Data CACHE via cachelink in Microblaze and mch_opb_ddr. Do you know how many cycles it takes to read the data from I/O? Access to OPB via IPIF (used by opb_gpio) may take 5 or 6 clock cycles. Consider also to use a DMA and enable burst in the memory controller. Claudio ----- Original Message ----- From: mencdaniele at tiscali.itmencdaniele at t...> To: Date: Tue Oct 10 15:19:20 CEST 2006 Subject: [oc] Help with Microblaze