1/1 
|
Quick Start on Opensource FPGA design VLSI Tools
by Unknown on Dec 14, 2006 |
Not available! | ||
|
hi
how we split a clock in to subclock (i.e.divided by 2,3, 4) using VHDL. If you can't divide a clock by 2 or 4 then you need to go back to reading VHDL for Dummies as this is very very basic stuff. Dividing a clock by 3 with a 1 to 2 mark to space ratio is also very easy. Dividing a clock by 3 with a 1 to 1 mark to space ratio is hard and requires use of some VHDL Voodoo. Post back here when you have worked out how to do the easy things and I'll give you some hints on how to this final thing. Colin. |
|||
|
Quick Start on Opensource FPGA design VLSI Tools
by Unknown on Dec 14, 2006 |
Not available! | ||
|
hi
how we split a clock in to subclock (i.e.divided by 2,3, 4) using VHDL.
----- Original Message -----
From: Shehryar Shaheenshehryar.shaheen at u...>
To:
Date: Sat May 15 17:10:09 CEST 2004
Subject: [oc] Quick Start on Opensource ASIC design VLSI Tools
Ofcourse the Alliance tools cannot be compared with Synopsys DC
or Cadence Buildgates etc but theses tools have big price tags
which
the Allaince tools don't. Its common knowledge that free tools may
not be wholly at par with the ones that are not free but then this
doesn't mean that nomenclature has to be different
Icarus Verilog is grouped under 'Verilog Simulator' but because
it doesn't have all the features that NC-Verilog or Verilog-XL have
it doesn't need to called say 'half-verilog simulator' or something
, now
does it :)
Alliance tools are free and are opensourse and yes they place
some amount of restrictions as to the way RTL is written but
then RTL is always written with strict rules keeping mind what
the synthesis tools will infer from the RTL.
Even Design Compiler or some other high end (and not free) tools
will not allow for absolute freedom to write what ever construct
one
feels like that is part of VHDL or Verilog language and the
synthesis
tools doesn't complain about it and one still might have to do
changes in the code to get it synthsized.
While they do support a larger synthesizable subset they are
neither free nor opensource.
----- Original Message -----
From: "Guy Hutchison" ghutchis at g...>
To: "Discussion list about free open source IP cores"
cores at o...>
Sent: Saturday, May 15, 2004 7:17 AM
Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools
> That essentially IS logic sysnthesis of standard VHDL RTL
> aftet this you get a VHDL gatelevel netlist made up with > standrad cells from the library sxlib ( sxlib is distributed with Allance)
>
> Unforunately, neither Verilog nor VHDL has ever defined what portion
> of the language constitutes the synthesizable subset, and so
we are
> left with de facto standards. The bar for this is whatever
VHDL code
> can be accepted by common synthesis tools as Design Compiler
and
> Get2Chip. While VASY does support more constructs than I
thought it
> did, it was unable to translate several VHDL files (from
> opencores.org) which I have previously compiled with DC. > > This means that, in practice, unless you are coding specifically for
> the Alliance tool set, compiling your code with VASY will
require
> rewriting substantial portions of it.
> > My comment about being misleading was that if you make a statement
> like "tool XXX supports logic synthesis" with no
conditions or
> caveats, anyone looking at the tool will expect it to have
roughly the
> same capabilities and limitations of other tools that support
logic
> synthesis; VASY/BOOM does not meet these criteria.
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
|
|||
1/1