OpenCores
Home » All forums » Cores » Crossbar Switch in Verilog HDL
no use no use 1/1 no use no use
Crossbar Switch in Verilog HDL
by Unknown on Dec 21, 2006 		Not available!
Hello: I am looking for a crossbar switch core (processor) design in verilog HDL. Specification: 5x5 with input or output buffering. Would you please point me to some papers or source code link. Thanks a lot Ben -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20061221/764bf8c0/attachment.htm
Crossbar Switch in Verilog HDL
by Unknown on Dec 22, 2006 		Not available!
Hello: I am looking for a crossbar switch core (processor) design in verilog HDL. Specification: 5 ports with inputs or outputs buffering Would you please point me to some work or source code link. Thanks a lot Ben -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20061222/013a764b/attachment.htm
no use no use 1/1 no use no use
© copyright 1999-2026 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.