Hello! I have greate interest in microprogramming unit (like sequencers and processors) realisation based om FPGA. Especialy I interesting in high-performance microprogramming units. I would like to see documentation about VLIW core and maybe take a part in this project, like hardware developer. I have some expirience and some developed units in this theme. Denis Shekhalev. -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of cores-request at opencores.org Sent: Thursday, December 21, 2006 7:36 PM To: cores at opencores.org Subject: Cores Digest, Vol 37, Issue 2 Send Cores mailing list submissions to cores at opencores.org To subscribe or unsubscribe via the World Wide Web, visit http://www.opencores.org/mailman/listinfo/cores or, via email, send a message with subject or body 'help' to cores-request at opencores.org You can reach the person managing the list at cores-owner at opencores.org When replying, please edit your Subject line so it is more specific than "Re: Contents of Cores digest..." Today's Topics: 1. Re: About Open Source VLIW core (dannoritzer) 2. use ofFFT core with quartus (fahim.abdullah at gmail.com) 3. Re: Quick Start on Opensource FPGA design VLSI Tools (khantauheed at gmail.com) 4. RE: Quick Start on Opensource FPGA design VLSI Tools (Colin Bathe) 5. Remportez un s?jour pour deux ? Hollywood ! (Bouygues Telecom) 6. Re: MP3 Decoder in VHDL (syuyang at gmail.com) 7. Re: MP3 Decoder in VHDL (djo8070) 8. Crossbar Switch in Verilog HDL (Ben A. Abderazek) ---------------------------------------------------------------------- Message: 1 Date: Tue, 12 Dec 2006 12:13:00 +0100 From: dannoritzer dannoritzer at web.de> Subject: Re: [oc] About Open Source VLIW core To: Discussion list about free open source IP cores cores at opencores.org> Message-ID: 457E8EBC.90707 at web.de> Content-Type: text/plain; charset=ISO-8859-1 Benjamin Jung wrote: You can draw a document over the web.archive.org: http://web.archive.org/web/*/http://home.att.net/~tekhknowledge/ Unfortunately the source downloads do not work. Cheers, Guenter ------------------------------ Message: 2 Date: Thu, 14 Dec 2006 12:01:25 +0100 (CET) From: fahim.abdullah at gmail.com Subject: [oc] use ofFFT core with quartus To: cores at opencores.org Message-ID: 20061214110125.EDF0D4C2B5 at www.opencores.org> Hi friends, I want to substract a particular bias from the spectrum of of a wav file. So I got the FFT program and subtract program (in verilog HDL). Now the problem is I don't know how to give wav (sound) input to the FFT program. Plz anyone help me .. -abd ------------------------------ Message: 3 Date: Thu, 14 Dec 2006 17:50:05 +0100 (CET) From: khantauheed at gmail.com Subject: Re: [oc] Quick Start on Opensource FPGA design VLSI Tools To: cores at opencores.org Message-ID: 20061214165005.2C4A54C2B5 at www.opencores.org> hi how we split a clock in to subclock (i.e.divided by 2,3, 4) using VHDL. ----- Original Message ----- From: Shehryar Shaheenshehryar.shaheen at u...> To: Date: Sat May 15 17:10:09 CEST 2004 Subject: [oc] Quick Start on Opensource ASIC design VLSI Tools ------------------------------ Message: 4 Date: Thu, 14 Dec 2006 16:06:50 -0000 From: "Colin Bathe" colin.opencores.cores at scitec.uk.com> Subject: RE: [oc] Quick Start on Opensource FPGA design VLSI Tools To: "Discussion list about free open source IP cores" cores at opencores.org> Message-ID: PHEDLCCPJAKFGPPEHNLDEECAGGAA.colin.opencores.cores at scitec.uk.com> Content-Type: text/plain; charset="iso-8859-1" If you can't divide a clock by 2 or 4 then you need to go back to reading VHDL for Dummies as this is very very basic stuff. Dividing a clock by 3 with a 1 to 2 mark to space ratio is also very easy.. Dividing a clock by 3 with a 1 to 1 mark to space ratio is hard and requires use of some VHDL Voodoo. Post back here when you have worked out how to do the easy things and I'll give you some hints on how to this final thing. Colin. ------------------------------ Message: 5 Date: Thu, 14 Dec 2006 21:38:08 +0100 From: Bouygues Telecom bouygues at in29.com> Subject: [oc] Remportez un s?jour pour deux ? Hollywood ! To: "cores at opencores.org" cores at opencores.org> Message-ID: 884a226e0f3bf60a886e9d13b76678ec at localhost.localdomain> Content-Type: text/plain; charset="iso-8859-1" Si vous dИsirez visualiser ce mail au format html, recopiez l'adresse suivante dans votre navigateur: http:///view.html?id=2829&ref=506910 Si vous dИsirez vous dИsinscrire, il suffit de cliquer sur le lien prИvu ou de recopier l'adresse suivante dans votre navigateur: http:///desabo.html?ope=2829&email=cores@opencores.org&client=31 -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20061214/ff21a747/attachment-0001.html ------------------------------ Message: 6 Date: Sun, 17 Dec 2006 22:20:06 +0100 (CET) From: syuyang at gmail.com Subject: Re: [oc] MP3 Decoder in VHDL To: cores at opencores.org Message-ID: 20061217212006.45EF24C2B0 at www.opencores.org> Hello, I am working on mp3 decoder for my cource project recently. I have surveyed lots of paper, standard about mp3 decoder process, but still didn't know how to implement. Did anyone have the source code in verilog or VHDL, can send to me. That would be very helpful!!! mail:syuyang at gmail.com ----- Original Message ----- From: penny1waypenny1way at y...> To: Date: Wed Sep 13 07:22:44 CEST 2006 Subject: [oc] MP3 Decoder in VHDL