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Physical design rules error during mapping with Xilinx8.1i
by aniket on Jan 18, 2007 |
aniket
Posts: 1 Joined: Dec 5, 2008 Last seen: Jun 11, 2013 |
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Hi
i am having problems with trying to generate a bitfile for my design. I am using Xilinx 8.1i and it is reporting the following errors during mapping and place and route. ERROR: PhysDesignrules:760 - Incompatible programming for IO Standard. IO Standard LVDS_25 of comp IO_x_x_x_X_x_x_x/iobuf_dqs/ IO does not allow both input and output programming on the same comp. Does anyone know anything about this error? |
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Physical design rules error during mapping with Xilinx8.1i
by Unknown on Jan 18, 2007 |
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On Wednesday 17 January 2007 20:35, aniket at asic-architectinc.com wrote:
i am having problems with trying to generate a bitfile for my design.
You apparently are using an IOBUF for an LVDS signal, which is illegal.
--
Wesley J. Landaker wjl at icecavern.net> wjl at icecavern.net>
OpenPGP FP: 4135 2A3B 4726 ACC5 9094 0097 F0A9 8A4C 4CD6 E3D2
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I am using Xilinx 8.1i and it is reporting the following errors during mapping and place and route. ERROR: PhysDesignrules:760 - Incompatible programming for IO Standard. IO Standard LVDS_25 of comp IO_x_x_x_X_x_x_x/iobuf_dqs/ IO does not allow both input and output programming on the same comp. Does anyone know anything about this error? |
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