This is a AES Rijndael IP core written in verilog. This is a complete implementation cipher, inverse cipher and 128 bit key expansion. I know there is another AES Rijndael project going on, which is in VHDL. It has been going on for 8 months now and is still not complete. I could not reach the 3 authors via email, so I just wrote my own version (took me only 5 days !). Cheers ! rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores: http://www.asics.ws/free_ip.shtml ----- ALL SPAM forwarded to: UCE at F... -----