On 1/19/07, edb6628 at hotmail.com edb6628 at hotmail.com> wrote:


This one has me scratching my head. How do you connect an MII MAC to an
RMII MAC? MII has 4 SDR data pins per direction, while RMII has 2 DDR pins
per direction.

I am looking for either Verilog code or ideas on the best way to
Depends on how concerned you are about speed, and how you're going to glue them together. Creating a digital PHY for 10Mbit rates is do-able. I haven't looked into how MLT is implemented for 100Mbit PHYs but believe it to be considerably more difficult. If you're just trying to get the devices to talk to each other in a timing-safe manner, I would just use a small FPGA to capture and re-time each side. - Guy -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20070120/76fcc899/attachment.htm

On Fri, 19 Jan 2007 13:10:08 -0800 "Guy Hutchison" ghutchis at gmail.com> wrote:

Xilinx has an appnote on how to convert GMII to RGMII. Basically you
just need a layer of external DDR registers with some simple logic. So,
I guess when the OP said the parts are connected back-to-back he omitted
this little detail. Personally I think adding a PHY layer in this
application would be a HUGE overkill.



/Mikhail

On 1/19/07, Mikhail Matusov misoma at rogers.com> wrote: Yes, but GMII -> RGMII conversion is much simpler, since both use source-synchronous clocking. Converting MII and RMII is more difficult since RMII has source-sync clocking and MII is system-side clocked in both directions. Some sort of async FIFO would be needed to do it correctly. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20070120/0ca4a7ed/attachment.htm

Hello,
I have inherited a design with two MACS connected to back to back.
One MAC interface is MII and the other is RMII. Both devices are
configured as MACs. Although, this violates the MII specification, it
is working, but I don't want to continue to press my luck.

I certainly can see an issue where the two MACs are MII compliant and
since the RX hold time of 10ns can not be guaranteed when TX is 0-25ns
from the rising edge of clock. This is the case with the network
processor on board:

NP RX setup=5.5ns hold=0ns

BME TX delay=0-25ns – no issue since NP hold =0

NP TX delay=17ns hold=2ns

BME RX setup=10ns hold=10ns – 8ns timing margin violation on hold time.

For MII compliant phys the RX sigs change on the falling-edge of the
clock so a violation is always avoided.

I am looking for either Verilog code or ideas on the best way to
implement Ethernet PHY functionality between these two devices.

Thank you
EB

True, my apologies. It is currently configured as MII to MII. Newer revisions of the BME revealed that the interface on the BME has changed from MII to RMII. Implementing a 100Mb PHY is not a trivial task, this is why I was asking. I have seen an article at Comms Design: http://www.commsdesign.com/showArticle.jhtml;jsessionid=FAG3F3AMSLDPQQSNDLQCKHSCJUNN2JVN?articleID=192200605 as a place to start but again it is MII to MII. Thanks ----- Original Message ----- From: Guy Hutchisonghutchis at g...> To: Date: Fri Jan 19 22:10:08 CET 2007 Subject: [oc] Implementing Ethernet PHY in Verilog

----- Original Message ----- From: Mikhail Matusovmisoma at r...> To: Date: Fri Jan 19 22:24:43 CET 2007 Subject: [oc] Implementing Ethernet PHY in Verilog True, my apologies. It is currently configured as MII to MII. Newer revisions of the BME revealed that the interface on the BME has changed from MII to RMII. Implementing a 100Mb PHY is not a trivial task, this is why I was asking. I have seen an article at Comms Design: http://www.commsdesign.com/showArticle.jhtml;jsessionid=FAG3F3AMSLDPQQSNDLQCKHSCJUNN2JVN?articleID=192200605 as a place to start but again it is MII to MII. -E