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Rei want to know the defrient of paralle and serial devies
by Unknown on Feb 3, 2007 |
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what is the defrient of parallel and serial devies
----- Original Message -----
From: John Sheahan jrsheahan at o...>
To: cores at o...
Date: Mon, 20 Jan 2003 20:41:17 +1100
Subject: Re: [oc] Real newbie questions
On Mon, Jan 20, 2003 at 11:46:03AM +0800, Niclas Hedhman wrote:
> a flow from schematic to vhdl to fpga would make little
sense.
>
> Well it makes sense to "Schematic people"... I look at VHDL and although being
> a programmer in every language from assembly to Java, VHDL is
obscure or
> should I say "hard to get my head around".
verilog is cleaner and more concise for me. But this is a religious issue. Yes - RTL is different to schematic. It takes some head rearrangement. But its time well spent. Compare a 32 bit adder in schematic and rtl and tell me which is more obvious. Or a state machine. Than change the adder to 48 bits.. I suspect schematic adherents for digital design are now few and far between - particularly in those doing any regular not-tiny design. The which-language wars are very much ongoing though :) Also consider the simulation testbench. Once you are used to using the same language for the TB as for the code - you won't want to go back to schematics and a separate sim language. Actually thats _almost_ the same language. You use a very different style in the TB. That does not have to synthesize efficiently.
>
> In a schematic - you have to instantiate paricular devies
- chosen
> from a library. What library did you use? thats the
device you have
> targetted. Perhaps there are several sized members
availave.
>
> I have several choice. For Altera and Xilinx there are libraries for different
> families, such as Spartan II(E), but there is also a more
"generic" CUPL
> library, which is a smaller subset (which does fine for me).
I have no idea how CUPL has changed - but it was pretty limited 15 years ago. And seems to hve become much less common. Reusing design modules is nice. I generally don't know what I will reuse. And over time the family changes. I have plenty of old xilinx 3000 - family schematics that are completely obselete. Its not the logic thats old - its the format.
>
> ypu my be able to get a structural gate vhdl netlist out
- thats
> exuivilant to disassembling compiled code. May be useful
for debug
> - but not very useful to port to a new architecture.
> > Write VHDL or Verilog RTL with any decent editor (with support for the
> language) Synthesize with the free (beer) tools from
Xilinx or Altera.
> I don't think schematic capture for fpga is of much
relevance any more.
>
> I will make it a shot. I will also try the synthesize tools and see how they
> react to the VHDL/CUPL netlist (and half a dozen FPGA related
formats) that
> Protel outputs.
> if its structural (ie connect this gate to that flop - there is nothing for the synthesis tool to do. You have _chosen_ the gate. RTL can be targetted. It may work - post a fragment of the CUPL vhdl output. Its possible for you and/or the tools to produce either. GAte level coding probably should only happen now to wring the last gate or ps out of a specific technology. And even then its often hard to justify.
> Those tools will also allow you to fit the design into
any of the
> ranges of parts they make. 192 bits of fifo is tiny -
will go into
> most any fpga and some cpld's. (unless you are doing
horrible
> clocking)
> > "Clocking"? Well, the building blocks are Serial-to-Parallel and
> Parallel-to-Serial shifters. Separate async input and output
clocks. (Input
> is dictated by the A/D converter at a continous 1Mbps stream,
while the
> output is to CPU over SPI Master at 2-5Mbps, when buffer is
filled.) A fifo - particularly fall-thru fifo can have very odd clocking. The more clocks the more issues you will have in a bunch of areas. And the harder the STA is . Sometimes you have to do more than one
clock, but its usually better to avoid that in any single module.
sounds like an application for block ram in a xilinx or altera.
>
> Anyway. Thanks for the advice. I'll get some books on the subject as well.
> A search on freashmeat.net for "VHDL Editor" only reveals
ChipVault for
> organization management, and "j" for syntax highlighting (The
Kate editor in
> Linux KDE 3.0 has VHDL and Verilog highlighting).
> I'll do more extensive searches, but are there any better tools (beyond syntax
> highlighting) available??
I use xemacs (or just emacs) with syntax highlighting, punctuation aware indenting and especially auto filling in of port lists and instantiations. But then emacs is also in the religion category... |
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