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CAN Controller
by Unknown on Feb 5, 2007 |
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Hi,
I'm using the verilog version of can_top and I fail to read out any receive data out of can_fifo except for the first message. I am using extended mode, and i did not forget to set the release buffer bit. I wonder how the length_info register shall be used. There is a signal called initialize_memories, its value starts with 1 and wont change until there is a write_info_pointer overrun (since : if(&write_info_pointer) init_mem because of this my length info used to be 0 in each register all the time, which might be the desired result of that memory initialisation. How do you do that usually when you restart your can controller, do you send some dummy messages at the start? I dared to change the after reset value of init_memories from 1 to 0 and I used Model Sim to check the result. In my test, the first message I write into the fifo has a length of 5 byte (no real message with id, just simulating the fifo module) and the second one has a length of 4 byte. The contents of the fifo is expectedly those written 9 bytes and the contents of the length_fifo register is 1st byte: 5, 2nd byte: 4. So far so good, but I dont see how reading out the messages will work in that case, since the read_info_pointer is incremented after each clk where there is a release_buffer signal, so after I read out the first byte of fifo (lets say address 16 which would be address 0 of fifo) the next read_address will already be address + 4 (fifo adddress 20+x) and I havent even read the second byte of the first message (fifo address 17). Where am I mistaken and how can I manage to read out the messages one by one? Hope anyone can understand my problem. Thanks for any helpful answer! Flex |
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CAN Controller
by Unknown on Feb 7, 2007 |
Not available! | ||
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Hi again, I think I was able to understand the problem myself.
Anyway, I had to make some changes to make it work under my
conditions, and to give any sense to this thread I will tell you what
kind of changes I made.
It is the release_buffer signal that caused my trouble because (,at
first I misunderstood its meaning and thought it had to be active for
each byte I want to read out,) I didn't see how to force it to be 1
for only one clk cycle, since I cannot give exact timing to my
incomming signals so far.
I altered the name of the input signal to
input release_buffer_request
I added a register
reg release_buffer_request_q
and another wire which is due to deliver the actual release_buffer
wire release_buffer
all other occurences of release_buffer stay just as they are and the
only thing missing now is:
assign release_buffer = release_buffer_request &
(~release_buffer_request_q);
always @ (posedge clk or posedge rst)
begin
if(rst)
release_buffer_request_q Flexie at g...>
To:
Date: Mon Feb 5 16:41:49 CET 2007
Subject: [oc] CAN Controller
Hi,
I'm using the verilog version of can_top and I fail to read out any receive data out of can_fifo except for the first message. I am using extended mode, and i did not forget to set the release buffer bit. I wonder how the length_info register shall be used. There is a signal called initialize_memories, its value starts with 1 and wont change until there is a write_info_pointer overrun (since : if(&write_info_pointer) init_mem because of this my length info used to be 0 in each register all the time, which might be the desired result of that memory initialisation. How do you do that usually when you restart your can controller, do you send some dummy messages at the start? I dared to change the after reset value of init_memories from 1 to 0 and I used Model Sim to check the result. In my test, the first message I write into the fifo has a length of 5 byte (no real message with id, just simulating the fifo module) and the second one has a length of 4 byte. The contents of the fifo is expectedly those written 9 bytes and the contents of the length_fifo register is 1st byte: 5, 2nd byte: 4. So far so good, but I dont see how reading out the messages will work in that case, since the read_info_pointer is incremented after each clk where there is a release_buffer signal, so after I read out the first byte of fifo (lets say address 16 which would be address 0 of fifo) the next read_address will already be address + 4 (fifo adddress 20+x) and I havent even read the second byte of the first message (fifo address 17). Where am I mistaken and how can I manage to read out the messages one by one? Hope anyone can understand my problem. Thanks for any helpful answer! Flex |
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