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Async reset: active high or active low?

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Async reset: active high or active low? by dude on Feb 7, 2007			dude Posts: 1 Joined: Jul 19, 2009 Last seen: Sep 19, 2009
He's right. There will be current drain between the high signal and ground which is a waste. ----- Original Message ----- From: Rudolf Usselmann <<A HREF="http://www.opencores.org/mailman/listinfo/cores">rudi at a...</A>> To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at o...</A> Date: 27 Apr 2003 15:33:27 +0700 Subject: Re: [oc] Async reset: active high or active low? [q] On Sun, 2003-04-27 at 14:48, Haytham Azmi wrote: [q]> Hi Nicolas , > I don't agree with you , i think it must be active [/q] high for [q]> many reasons .. > 1- At power up it's normal for all system to reset [/q] , this is [q]> the normal case and then , start executing the [/q] main [q]> program . > 2- If we put the reset active low , that means you [/q] have to [q]> put high at the reset signal during normal mode [/q] , and [q]> that will be a sourcefor power loss ... so it's [/q] better [q]> to make it active high . [/q] Hugh ? Source for power loss ? Not if you designing in CMOS. It "consumes" power when it switches from one level to the other. If you do not switch (change logic levels) power consumption should be very close to zero (in any practical terms anyway). [q]> 3- I think you can check for any microcontrolle [/q] datasheet [q]> you will see that the reset is active high . > > If iam wrong please correct my information. > > Best [/q] redards, [q]> Haytham [/q] In my opinion it should be absolutely irrelevant if reset is active high or low. Use an inverter - the synthesis tool might turn the level around anyway, because of your synthesis library constrains (e.g. only active low asycn reset flops are available) and insert an inverter if it needs to. For IP cores that you want to be used/re-used by others I have two suggestions: 1) Make the Level of the reset user selectable: for example: `define ACT_RST_LEVEL 1'b1 // Active HIGH `define ACT_RST_LEVEL 1'b0 // Active LOW always @(posedge clk) if(my_reset == `ACT_RST_LEVEL) my_flop <= 1'b0; else my_flop <= din; 2) Make the type of the reset (sync/async) also user selectable: for example: `define ACT_RST_LEVEL 1'b1 // Active HIGH `define ACT_RST_LEVEL 1'b0 // Active LOW `define ASYNC_RST or posedge my_reset // Asynchronous High Active `define ASYNC_RST or negedge my_reset // Asynchronous Low Active `define ASYNC_RST // Synchronous Reset NOTE: Make sure ACT_RST_LEVEL matches the async reset definition !!! always @(posedge clk `ASYNC_RST) if(my_reset == `ACT_RST_LEVEL) my_flop <= 1'b0; else my_flop <= din; One of these days I will go through all of my cores and implement the above in all of them ! Cheers ! rudi ------------------------------------------------------- www.asics.ws -- Solutions for your ASIC/FPGA needs --- ---------------- FPGAs * Full Custom ICs * IP Cores --- * * * FREE IP Cores --> <A HREF="http://www.asics.ws/">http://www.asics.ws/</A> <-- * * * [/q] He's right. There will be current drain between the high signal and ground which is a waste. ----- Original Message ----- From: Rudolf Usselmann rudi at a...> To: cores at o... Date: 27 Apr 2003 15:33:27 +0700 Subject: Re: [oc] Async reset: active high or active low? On Sun, 2003-04-27 at 14:48, Haytham Azmi wrote: > Hi Nicolas , > I don't agree with you , i think it must be active high for > many reasons .. > 1- At power up it's normal for all system to reset , this is > the normal case and then , start executing the main > program . > 2- If we put the reset active low , that means you have to > put high at the reset signal during normal mode , and > that will be a sourcefor power loss ... so it's better > to make it active high . Hugh ? Source for power loss ? Not if you designing in CMOS. It "consumes" power when it switches from one level to the other. If you do not switch (change logic levels) power consumption should be very close to zero (in any practical terms anyway). > 3- I think you can check for any microcontrolle datasheet > you will see that the reset is active high . > > If iam wrong please correct my information. > > Best redards, > Haytham In my opinion it should be absolutely irrelevant if reset is active high or low. Use an inverter - the synthesis tool might turn the level around anyway, because of your synthesis library constrains (e.g. only active low asycn reset flops are available) and insert an inverter if it needs to. For IP cores that you want to be used/re-used by others I have two suggestions: 1) Make the Level of the reset user selectable: for example: `define ACT_RST_LEVEL 1'b1 // Active HIGH `define ACT_RST_LEVEL 1'b0 // Active LOW always @(posedge clk) if(my_reset == `ACT_RST_LEVEL) my_flop http://www.asics.ws/

Async reset: active high or active low? by Unknown on Feb 8, 2007			Not available!
hi.. can any one help me there .... :-( i need to know where can i find open codes available for designing in FPGAs.. i wana design DFT in fpga... help me..plzz.... On 2/8/07, <A HREF="http://www.opencores.org/mailman/listinfo/cores">dude at something.com</A> <<A HREF="http://www.opencores.org/mailman/listinfo/cores">dude at something.com</A>> wrote: [q] He's right. There will be current drain between the high signal and ground which is a waste. ----- Original Message ----- From: Rudolf Usselmann <<A HREF="http://www.opencores.org/mailman/listinfo/cores">rudi at a...</A>> To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at o...</A> Date: 27 Apr 2003 15:33:27 +0700 Subject: Re: [oc] Async reset: active high or active low? [q]> > > On Sun, 2003-04-27 at 14:48, Haytham Azmi wrote: [q] > Hi Nicolas , > I don't agree with you , i think it must be active[/q] > high for [q] > many reasons .. > 1- At power up it's normal for all system to reset[/q] > , this is [q] > the normal case and then , start executing the[/q] > main [q] > program . > 2- If we put the reset active low , that means you[/q] > have to [q] > put high at the reset signal during normal mode[/q] > , and [q] > that will be a sourcefor power loss ... so it's[/q] > better [q] > to make it active high .[/q] > > Hugh ? Source for power loss ? > > Not if you designing in CMOS. It "consumes" power > when it switches from one level to the other. If > you do not switch (change logic levels) power > consumption should be very close to zero (in any > practical terms anyway). > [q] > 3- I think you can check for any microcontrolle[/q] > datasheet [q] > you will see that the reset is active high . > > If iam wrong please correct my information. > > Best[/q] > redards, [q] > Haytham[/q] > > In my opinion it should be absolutely irrelevant if reset > is active high or low. Use an inverter - the synthesis tool > might turn the level around anyway, because of your synthesis > library constrains (e.g. only active low asycn reset flops > are available) and insert an inverter if it needs to. > > For IP cores that you want to be used/re-used by others I have > two suggestions: > > 1) Make the Level of the reset user selectable: > > for example: > > `define ACT_RST_LEVEL 1'b1 // Active HIGH > `define ACT_RST_LEVEL 1'b0 // Active LOW > > always @(posedge clk) > if(my_reset == `ACT_RST_LEVEL) my_flop <= 1'b0; > else my_flop <= din; > > > 2) Make the type of the reset (sync/async) also user selectable: > > for example: > > `define ACT_RST_LEVEL 1'b1 // Active HIGH > `define ACT_RST_LEVEL 1'b0 // Active LOW > > `define ASYNC_RST or posedge my_reset // Asynchronous High Active > `define ASYNC_RST or negedge my_reset // Asynchronous Low Active > `define ASYNC_RST // Synchronous Reset > > NOTE: Make sure ACT_RST_LEVEL matches the async reset definition > !!! > > always @(posedge clk `ASYNC_RST) > if(my_reset == `ACT_RST_LEVEL) my_flop <= 1'b0; > else my_flop <= din; > > > One of these days I will go through all of my cores and > implement the above in all of them ! > > Cheers ! > rudi > ------------------------------------------------------- > www.asics.ws -- Solutions for your ASIC/FPGA needs --- > ---------------- FPGAs * Full Custom ICs * IP Cores --- > * * * FREE IP Cores --> <A HREF="http://www.asics.ws/">http://www.asics.ws/</A> <-- * * * >[/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] -------------- next part -------------- An HTML attachment was scrubbed... URL: <A HREF="http://www.opencores.org/forums.cgi/cores/attachments/20070208/29c1d2e7/attachment.htm">http://www.opencores.org/forums.cgi/cores/attachments/20070208/29c1d2e7/attachment.htm</A> hi.. can any one help me there .... :-( i need to know where can i find open codes available for designing in FPGAs.. i wana design DFT in fpga... help me..plzz.... On 2/8/07, dude at something.com dude at something.com> wrote: He's right. There will be current drain between the high signal and ground which is a waste. ----- Original Message ----- From: Rudolf Usselmann rudi at a...> To: cores at o... Date: 27 Apr 2003 15:33:27 +0700 Subject: Re: [oc] Async reset: active high or active low? > > > On Sun, 2003-04-27 at 14:48, Haytham Azmi wrote: > Hi Nicolas , > I don't agree with you , i think it must be active > high for > many reasons .. > 1- At power up it's normal for all system to reset > , this is > the normal case and then , start executing the > main > program . > 2- If we put the reset active low , that means you > have to > put high at the reset signal during normal mode > , and > that will be a sourcefor power loss ... so it's > better > to make it active high . > > Hugh ? Source for power loss ? > > Not if you designing in CMOS. It "consumes" power > when it switches from one level to the other. If > you do not switch (change logic levels) power > consumption should be very close to zero (in any > practical terms anyway). > > 3- I think you can check for any microcontrolle > datasheet > you will see that the reset is active high . > > If iam wrong please correct my information. > > Best > redards, > Haytham > > In my opinion it should be absolutely irrelevant if reset > is active high or low. Use an inverter - the synthesis tool > might turn the level around anyway, because of your synthesis > library constrains (e.g. only active low asycn reset flops > are available) and insert an inverter if it needs to. > > For IP cores that you want to be used/re-used by others I have > two suggestions: > > 1) Make the Level of the reset user selectable: > > for example: > > `define ACT_RST_LEVEL 1'b1 // Active HIGH > `define ACT_RST_LEVEL 1'b0 // Active LOW > > always @(posedge clk) > if(my_reset == `ACT_RST_LEVEL) my_flop else my_flop > > 2) Make the type of the reset (sync/async) also user selectable: > > for example: > > `define ACT_RST_LEVEL 1'b1 // Active HIGH > `define ACT_RST_LEVEL 1'b0 // Active LOW > > `define ASYNC_RST or posedge my_reset // Asynchronous High Active > `define ASYNC_RST or negedge my_reset // Asynchronous Low Active > `define ASYNC_RST // Synchronous Reset > > NOTE: Make sure ACT_RST_LEVEL matches the async reset definition > !!! > > always @(posedge clk `ASYNC_RST) > if(my_reset == `ACT_RST_LEVEL) my_flop else my_flop > > One of these days I will go through all of my cores and > implement the above in all of them ! > > Cheers ! > rudi > ------------------------------------------------------- > www.asics.ws -- Solutions for your ASIC/FPGA needs --- > ---------------- FPGAs * Full Custom ICs * IP Cores --- > * * * FREE IP Cores --> http://www.asics.ws/ _______________________________________________ http://www.opencores.org/mailman/listinfo/cores -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20070208/29c1d2e7/attachment.htm

Async reset: active high or active low? by Unknown on Feb 8, 2007			Not available!
Can you defend this position with numbers? there is lots of stuff connected to VDD in silicon that a low reset could leak to that you may be ignoring. john <A HREF="http://www.opencores.org/mailman/listinfo/cores">dude at something.com</A> wrote: [q] He's right. There will be current drain between the high signal and ground which is a waste. ----- Original Message ----- From: Rudolf Usselmann <<A HREF="http://www.opencores.org/mailman/listinfo/cores">rudi at a...</A>> To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at o...</A> Date: 27 Apr 2003 15:33:27 +0700 Subject: Re: [oc] Async reset: active high or active low? [q] On Sun, 2003-04-27 at 14:48, Haytham Azmi wrote: [q] Hi Nicolas , I don't agree with you , i think it must be active [/q] high for [q] many reasons .. 1- At power up it's normal for all system to reset [/q] , this is [q] the normal case and then , start executing the [/q] main [q] program . 2- If we put the reset active low , that means you [/q] have to [q] put high at the reset signal during normal mode [/q] , and [q] that will be a sourcefor power loss ... so it's [/q] better [q] to make it active high . [/q] Hugh ? Source for power loss ? Not if you designing in CMOS. It "consumes" power when it switches from one level to the other. If you do not switch (change logic levels) power consumption should be very close to zero (in any practical terms anyway). [q] 3- I think you can check for any microcontrolle [/q] datasheet [q] you will see that the reset is active high . If iam wrong please correct my information. Best [/q] redards, [q] Haytham [/q] In my opinion it should be absolutely irrelevant if reset is active high or low. Use an inverter - the synthesis tool might turn the level around anyway, because of your synthesis library constrains (e.g. only active low asycn reset flops are available) and insert an inverter if it needs to. For IP cores that you want to be used/re-used by others I have two suggestions: 1) Make the Level of the reset user selectable: for example: `define ACT_RST_LEVEL 1'b1 // Active HIGH `define ACT_RST_LEVEL 1'b0 // Active LOW always @(posedge clk) if(my_reset == `ACT_RST_LEVEL) my_flop <= 1'b0; else my_flop <= din; 2) Make the type of the reset (sync/async) also user selectable: for example: `define ACT_RST_LEVEL 1'b1 // Active HIGH `define ACT_RST_LEVEL 1'b0 // Active LOW `define ASYNC_RST or posedge my_reset // Asynchronous High Active `define ASYNC_RST or negedge my_reset // Asynchronous Low Active `define ASYNC_RST // Synchronous Reset NOTE: Make sure ACT_RST_LEVEL matches the async reset definition !!! always @(posedge clk `ASYNC_RST) if(my_reset == `ACT_RST_LEVEL) my_flop <= 1'b0; else my_flop <= din; One of these days I will go through all of my cores and implement the above in all of them ! Cheers ! rudi ------------------------------------------------------- www.asics.ws -- Solutions for your ASIC/FPGA needs --- ---------------- FPGAs * Full Custom ICs * IP Cores --- * * * FREE IP Cores --> <A HREF="http://www.asics.ws/">http://www.asics.ws/</A> <-- * * * [/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A>[/q] Can you defend this position with numbers? there is lots of stuff connected to VDD in silicon that a low reset could leak to that you may be ignoring. john dude at something.com wrote: He's right. There will be current drain between the high signal and ground which is a waste. ----- Original Message ----- From: Rudolf Usselmann rudi at a...> To: cores at o... Date: 27 Apr 2003 15:33:27 +0700 Subject: Re: [oc] Async reset: active high or active low? On Sun, 2003-04-27 at 14:48, Haytham Azmi wrote: Hi Nicolas , I don't agree with you , i think it must be active high for many reasons .. 1- At power up it's normal for all system to reset , this is the normal case and then , start executing the main program . 2- If we put the reset active low , that means you have to put high at the reset signal during normal mode , and that will be a sourcefor power loss ... so it's better to make it active high . Hugh ? Source for power loss ? Not if you designing in CMOS. It "consumes" power when it switches from one level to the other. If you do not switch (change logic levels) power consumption should be very close to zero (in any practical terms anyway). 3- I think you can check for any microcontrolle datasheet you will see that the reset is active high . If iam wrong please correct my information. Best redards, Haytham In my opinion it should be absolutely irrelevant if reset is active high or low. Use an inverter - the synthesis tool might turn the level around anyway, because of your synthesis library constrains (e.g. only active low asycn reset flops are available) and insert an inverter if it needs to. For IP cores that you want to be used/re-used by others I have two suggestions: 1) Make the Level of the reset user selectable: for example: `define ACT_RST_LEVEL 1'b1 // Active HIGH `define ACT_RST_LEVEL 1'b0 // Active LOW always @(posedge clk) if(my_reset == `ACT_RST_LEVEL) my_flop http://www.asics.ws/ _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Async reset: active high or active low? by Unknown on Feb 8, 2007			Not available!
As I recall from my (distant) board design days, the main reason for having an active-low reset is that it's easier to keep the reset asserted low during board power-on than to keep it high. Makes no difference for on-chip resets, though, since it's easy enough to invert when it comes on chip... - Guy -------------- next part -------------- An HTML attachment was scrubbed... URL: <A HREF="http://www.opencores.org/forums.cgi/cores/attachments/20070208/c9ee4a54/attachment.htm">http://www.opencores.org/forums.cgi/cores/attachments/20070208/c9ee4a54/attachment.htm</A> As I recall from my (distant) board design days, the main reason for having an active-low reset is that it's easier to keep the reset asserted low during board power-on than to keep it high. Makes no difference for on-chip resets, though, since it's easy enough to invert when it comes on chip... - Guy -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20070208/c9ee4a54/attachment.htm

Async reset: active high or active low? by Unknown on Feb 8, 2007			Not available!
Guy Hutchison wrote: [q] As I recall from my (distant) board design days, the main reason for having an active-low reset is that it's easier to keep the reset asserted low during board power-on than to keep it high. Makes no difference for on-chip resets, though, since it's easy enough to invert when it comes on chip...[/q] On 5V TTL designs, there's better noise margin on high levels, so it could occasionally make sense to have active-low signals. It makes no difference at all with CMOS. The OP should look at some CMOS I/O structures; they're symmetrical, with high-impedance inputs. I guess there could be trivial differences related to sizing of N and P channel transistors, or input protection structures, or excess leakage sub-90nm, but I've never heard of anyone using that as a basis for selecting a signal polarity. Amazing how a thread can go on for 3 years here... :) Guy Hutchison wrote: As I recall from my (distant) board design days, the main reason for having an active-low reset is that it's easier to keep the reset asserted low during board power-on than to keep it high. Makes no difference for on-chip resets, though, since it's easy enough to invert when it comes on chip... On 5V TTL designs, there's better noise margin on high levels, so it could occasionally make sense to have active-low signals. It makes no difference at all with CMOS. The OP should look at some CMOS I/O structures; they're symmetrical, with high-impedance inputs. I guess there could be trivial differences related to sizing of N and P channel transistors, or input protection structures, or excess leakage sub-90nm, but I've never heard of anyone using that as a basis for selecting a signal polarity. Amazing how a thread can go on for 3 years here... :)

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