Hi

I recently wrote a perl script for converting synthesizeable
verilog to vhdl.

It copes with most of the structures I use, but is bound to
suffer when other styles are involved.

Is there any interst is posting and assisting tweaking this?
I'd like fragments of code it has trouble with, and the expected
result (both if it works, and does not, for regression)

john

John,

Can you send me the tool to convert verilog code to vhdl?

Thanks Venu ----- Original Message ----- From: John Sheahan jrsheahan at o...> To: cores at o... Date: Fri, 4 Apr 2003 20:15:31 +1000 Subject: [oc] verilog to vhdl converter _______________________________________________ http://www.opencores.org/mailman/listinfo/cores