Hi all, on OpenCores there's the beta version of the S1 Core, a derivative design of the OpenSPARC T1 released by Sun Microsystems. The S1 is single core and features a wishbone master interface. At the moment the biggest problem with the S1 Core is probably a software issue, since while reading the OpenBoot code the SPARC Core inside the S1 the simulation hangs. The bug is detailed here: http://www.opencores.org/ptracker.cgi/view/s1_core/265 If you have some experience with OBP (OpenBoot PROM) you could probably help to find what's going wrong. Thanks in advance, Fabrizio -- ============================================ Fabrizio Fazzino - fabrizio at fazzino.it Fazzino.IT - http://www.fazzino.it ============================================