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Serial / UART link to host by Unknown on Mar 9, 2007			Not available!
<A HREF="http://www.opencores.org/mailman/listinfo/cores">manuel.kampert at online.de</A> wrote: [q] Hello![/q] [...] [q] I choosed the VHDL USART circuit from this forum and read the documentation. I was quite impressed about the complexity of this module and was unable to figure out how to just send some single bytes to my machine. [/q] Maybe I overlooked one, but do you mean the Serial UART <A HREF="http://www.opencores.org/projects.cgi/web/uart">http://www.opencores.org/projects.cgi/web/uart</A> or the UART 16550 <A HREF="http://www.opencores.org/projects.cgi/web/uart16550">http://www.opencores.org/projects.cgi/web/uart16550</A> The first one has a VHDL testbench, the later one only a Verilog one. If there is nothing in the documentation, the test bench might be the best place to look how they feed data into the core. Cheers, Guenter [q] Does someone have some lines of code that would give me a start to initialize this circuit? Many Thanks, Manue. _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] manuel.kampert at online.de wrote: Hello! [...] I choosed the VHDL USART circuit from this forum and read the documentation. I was quite impressed about the complexity of this module and was unable to figure out how to just send some single bytes to my machine. Maybe I overlooked one, but do you mean the Serial UART http://www.opencores.org/projects.cgi/web/uart or the UART 16550 http://www.opencores.org/projects.cgi/web/uart16550 The first one has a VHDL testbench, the later one only a Verilog one. If there is nothing in the documentation, the test bench might be the best place to look how they feed data into the core. Cheers, Guenter Does someone have some lines of code that would give me a start to initialize this circuit? Many Thanks, Manue. _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Serial / UART link to host by Unknown on Mar 9, 2007			Not available!
Hello! I am new to the FPGA thing and also new to this forum - so please forgive me if I post to the wrong folder and point me to the direct one - My current project is to aquire some data via an ADC controller, put it to the SRAM and then send it to my PC. So far I have managed to get some data to the SRAM and thougth it would be fairly easy to transfer this data to my host pc. I choosed the VHDL USART circuit from this forum and read the documentation. I was quite impressed about the complexity of this module and was unable to figure out how to just send some single bytes to my machine. Does someone have some lines of code that would give me a start to initialize this circuit? Many Thanks, Manue. Hello! I am new to the FPGA thing and also new to this forum - so please forgive me if I post to the wrong folder and point me to the direct one - My current project is to aquire some data via an ADC controller, put it to the SRAM and then send it to my PC. So far I have managed to get some data to the SRAM and thougth it would be fairly easy to transfer this data to my host pc. I choosed the VHDL USART circuit from this forum and read the documentation. I was quite impressed about the complexity of this module and was unable to figure out how to just send some single bytes to my machine. Does someone have some lines of code that would give me a start to initialize this circuit? Many Thanks, Manue.

Serial / UART link to host by Unknown on Mar 9, 2007			Not available!
Use uart16550 in Verilog. This version works fine. I'm not sure for other versions. Regards, Igor On 3/9/07, <A HREF="http://www.opencores.org/mailman/listinfo/cores">manuel.kampert at online.de</A> <<A HREF="http://www.opencores.org/mailman/listinfo/cores">manuel.kampert at online.de</A>> wrote: [q] The core that i've used was <A HREF="http://www.opencores.org/pdownloads.cgi/list/a_vhd_16550_uart">http://www.opencores.org/pdownloads.cgi/list/a_vhd_16550_uart</A> Unfortunately it did not contain any testbench. ----- Original Message ----- From: GÃ¼nter Dannoritzer<<A HREF="http://www.opencores.org/mailman/listinfo/cores">dannoritzer at w...</A>> To: Date: Fri Mar 9 14:00:39 CET 2007 Subject: [oc] Serial / UART link to host [q]> manuel.kampert at online.de wrote: [q] > Hello![/q] > [...] [q] > I choosed the VHDL USART circuit from this forum and read the > documentation. I was quite impressed about the complexity of[/q] > this [q] > module and was unable to figure out how to just send some[/q] > single bytes [q] > to my machine. >[/q] > Maybe I overlooked one, but do you mean the > Serial UART > <A HREF="http://www.opencores.org/projects.cgi/web/uart">http://www.opencores.org/projects.cgi/web/uart</A> > or the > UART 16550 > <A HREF="http://www.opencores.org/projects.cgi/web/uart16550">http://www.opencores.org/projects.cgi/web/uart16550</A> > The first one has a VHDL testbench, the later one only a Verilog > one. If > there is nothing in the documentation, the test bench might be the > best > place to look how they feed data into the core. > Cheers, > Guenter [q] > Does someone have some lines of code that would give me a[/q] > start to [q] > initialize this circuit? > > Many Thanks, > Manue. > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> >[/q] > >[/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] -------------- next part -------------- An HTML attachment was scrubbed... URL: <A HREF="http://www.opencores.org/forums.cgi/cores/attachments/20070309/c45754f5/attachment.htm">http://www.opencores.org/forums.cgi/cores/attachments/20070309/c45754f5/attachment.htm</A> Use uart16550 in Verilog. This version works fine. I'm not sure for other versions. Regards, Igor On 3/9/07, manuel.kampert at online.de manuel.kampert at online.de> wrote: The core that i've used was http://www.opencores.org/pdownloads.cgi/list/a_vhd_16550_uart Unfortunately it did not contain any testbench. ----- Original Message ----- From: GÃ¼nter Dannoritzerdannoritzer at w...> To: Date: Fri Mar 9 14:00:39 CET 2007 Subject: [oc] Serial / UART link to host > manuel.kampert at online.de wrote: > Hello! > [...] > I choosed the VHDL USART circuit from this forum and read the > documentation. I was quite impressed about the complexity of > this > module and was unable to figure out how to just send some > single bytes > to my machine. > > Maybe I overlooked one, but do you mean the > Serial UART > http://www.opencores.org/projects.cgi/web/uart > or the > UART 16550 > http://www.opencores.org/projects.cgi/web/uart16550 > The first one has a VHDL testbench, the later one only a Verilog > one. If > there is nothing in the documentation, the test bench might be the > best > place to look how they feed data into the core. > Cheers, > Guenter > Does someone have some lines of code that would give me a > start to > initialize this circuit? > > Many Thanks, > Manue. > _______________________________________________ > http://www.opencores.org/mailman/listinfo/cores > > > _______________________________________________ http://www.opencores.org/mailman/listinfo/cores -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20070309/c45754f5/attachment.htm

Serial / UART link to host by Unknown on Mar 9, 2007			Not available!
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Serial / UART link to host by Unknown on Mar 9, 2007			Not available!
This BSD page has some good information on the standard UART register set. In general your FPGA will need to have either a small microprocessor or a state machine to program the initial parameters into the UART and then push data into and out of it. Link: <A HREF="http://www.freebsd.org/doc/en_US.ISO8859-1/articles/serial-uart/article.html">http://www.freebsd.org/doc/en_US.ISO8859-1/articles/serial-uart/article.html</A> - Guy On 3/9/07, <A HREF="http://www.opencores.org/mailman/listinfo/cores">manuel.kampert at online.de</A> <<A HREF="http://www.opencores.org/mailman/listinfo/cores">manuel.kampert at online.de</A>> wrote: [q] The core that i've used was <A HREF="http://www.opencores.org/pdownloads.cgi/list/a_vhd_16550_uart">http://www.opencores.org/pdownloads.cgi/list/a_vhd_16550_uart</A> Unfortunately it did not contain any testbench. ----- Original Message ----- From: GÃ¼nter Dannoritzer<<A HREF="http://www.opencores.org/mailman/listinfo/cores">dannoritzer at w...</A>> To: Date: Fri Mar 9 14:00:39 CET 2007 Subject: [oc] Serial / UART link to host [q]> manuel.kampert at online.de wrote: [q] > Hello![/q] > [...] [q] > I choosed the VHDL USART circuit from this forum and read the > documentation. I was quite impressed about the complexity of[/q] > this [q] > module and was unable to figure out how to just send some[/q] > single bytes [q] > to my machine. >[/q] > Maybe I overlooked one, but do you mean the > Serial UART > <A HREF="http://www.opencores.org/projects.cgi/web/uart">http://www.opencores.org/projects.cgi/web/uart</A> > or the > UART 16550 > <A HREF="http://www.opencores.org/projects.cgi/web/uart16550">http://www.opencores.org/projects.cgi/web/uart16550</A> > The first one has a VHDL testbench, the later one only a Verilog > one. If > there is nothing in the documentation, the test bench might be the > best > place to look how they feed data into the core. > Cheers, > Guenter [q] > Does someone have some lines of code that would give me a[/q] > start to [q] > initialize this circuit? > > Many Thanks, > Manue. > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> >[/q] > >[/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] -------------- next part -------------- An HTML attachment was scrubbed... URL: <A HREF="http://www.opencores.org/forums.cgi/cores/attachments/20070309/d1866461/attachment.htm">http://www.opencores.org/forums.cgi/cores/attachments/20070309/d1866461/attachment.htm</A> This BSD page has some good information on the standard UART register set. In general your FPGA will need to have either a small microprocessor or a state machine to program the initial parameters into the UART and then push data into and out of it. Link: http://www.freebsd.org/doc/en_US.ISO8859-1/articles/serial-uart/article.html - Guy On 3/9/07, manuel.kampert at online.de manuel.kampert at online.de> wrote: The core that i've used was http://www.opencores.org/pdownloads.cgi/list/a_vhd_16550_uart Unfortunately it did not contain any testbench. ----- Original Message ----- From: GÃ¼nter Dannoritzerdannoritzer at w...> To: Date: Fri Mar 9 14:00:39 CET 2007 Subject: [oc] Serial / UART link to host > manuel.kampert at online.de wrote: > Hello! > [...] > I choosed the VHDL USART circuit from this forum and read the > documentation. I was quite impressed about the complexity of > this > module and was unable to figure out how to just send some > single bytes > to my machine. > > Maybe I overlooked one, but do you mean the > Serial UART > http://www.opencores.org/projects.cgi/web/uart > or the > UART 16550 > http://www.opencores.org/projects.cgi/web/uart16550 > The first one has a VHDL testbench, the later one only a Verilog > one. If > there is nothing in the documentation, the test bench might be the > best > place to look how they feed data into the core. > Cheers, > Guenter > Does someone have some lines of code that would give me a > start to > initialize this circuit? > > Many Thanks, > Manue. > _______________________________________________ > http://www.opencores.org/mailman/listinfo/cores > > > _______________________________________________ http://www.opencores.org/mailman/listinfo/cores -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20070309/d1866461/attachment.htm

Serial / UART link to host by Unknown on Mar 9, 2007			Not available!
The core that i've used was <A HREF="http://www.opencores.org/pdownloads.cgi/list/a_vhd_16550_uart">http://www.opencores.org/pdownloads.cgi/list/a_vhd_16550_uart</A> Unfortunately it did not contain any testbench. ----- Original Message ----- From: GÃ¼nter Dannoritzer<<A HREF="http://www.opencores.org/mailman/listinfo/cores">dannoritzer at w...</A>> To: Date: Fri Mar 9 14:00:39 CET 2007 Subject: [oc] Serial / UART link to host [q] manuel.kampert at online.de wrote: [q]> Hello! [/q] [...] [q]> I choosed the VHDL USART circuit from this forum and read the > documentation. I was quite impressed about the complexity of [/q] this [q]> module and was unable to figure out how to just send some [/q] single bytes [q]> to my machine. > [/q] Maybe I overlooked one, but do you mean the Serial UART <A HREF="http://www.opencores.org/projects.cgi/web/uart">http://www.opencores.org/projects.cgi/web/uart</A> or the UART 16550 <A HREF="http://www.opencores.org/projects.cgi/web/uart16550">http://www.opencores.org/projects.cgi/web/uart16550</A> The first one has a VHDL testbench, the later one only a Verilog one. If there is nothing in the documentation, the test bench might be the best place to look how they feed data into the core. Cheers, Guenter [q]> Does someone have some lines of code that would give me a [/q] start to [q]> initialize this circuit? > > Many Thanks, > Manue. > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> > [/q] [/q] The core that i've used was http://www.opencores.org/pdownloads.cgi/list/a_vhd_16550_uart Unfortunately it did not contain any testbench. ----- Original Message ----- From: GÃ¼nter Dannoritzerdannoritzer at w...> To: Date: Fri Mar 9 14:00:39 CET 2007 Subject: [oc] Serial / UART link to host manuel.kampert at online.de wrote: > Hello! [...] > I choosed the VHDL USART circuit from this forum and read the > documentation. I was quite impressed about the complexity of this > module and was unable to figure out how to just send some single bytes > to my machine. > Maybe I overlooked one, but do you mean the Serial UART http://www.opencores.org/projects.cgi/web/uart or the UART 16550 http://www.opencores.org/projects.cgi/web/uart16550 The first one has a VHDL testbench, the later one only a Verilog one. If there is nothing in the documentation, the test bench might be the best place to look how they feed data into the core. Cheers, Guenter > Does someone have some lines of code that would give me a start to > initialize this circuit? > > Many Thanks, > Manue. > _______________________________________________ > http://www.opencores.org/mailman/listinfo/cores >

Serial / UART link to host by Unknown on Mar 10, 2007			Not available!
most of the uarts on opencores come with tons of features hat you love if you got a cpu connected, if you just need a single baud-rate no fifo features no handshakes (or only cts/dts) you are better of looking at something as simple as <A HREF="http://direct.xilinx.com/bvdocs/appnotes/xapp341.pdf">http://direct.xilinx.com/bvdocs/appnotes/xapp341.pdf</A> that gets communication up and running in a couple of hours. thilo Guy Hutchison wrote: [q] This BSD page has some good information on the standard UART register set. In general your FPGA will need to have either a small microprocessor or a state machine to program the initial parameters into the UART and then push data into and out of it. Link: <A HREF="http://www.freebsd.org/doc/en_US.ISO8859-1/articles/serial-uart/article.html">http://www.freebsd.org/doc/en_US.ISO8859-1/articles/serial-uart/article.html</A> - Guy On 3/9/07, <A HREF="http://www.opencores.org/mailman/listinfo/cores">manuel.kampert at online.de</A> <mailto:<A HREF="http://www.opencores.org/mailman/listinfo/cores">manuel.kampert at online.de</A>> <<A HREF="http://www.opencores.org/mailman/listinfo/cores">manuel.kampert at online.de</A> <mailto:<A HREF="http://www.opencores.org/mailman/listinfo/cores">manuel.kampert at online.de</A>>> wrote: The core that i've used was <A HREF="http://www.opencores.org/pdownloads.cgi/list/a_vhd_16550_uart">http://www.opencores.org/pdownloads.cgi/list/a_vhd_16550_uart</A> Unfortunately it did not contain any testbench. ----- Original Message ----- From: GÃ¼nter Dannoritzer<<A HREF="http://www.opencores.org/mailman/listinfo/cores">dannoritzer at w...</A>> To: Date: Fri Mar 9 14:00:39 CET 2007 Subject: [oc] Serial / UART link to host [q] > manuel.kampert at online.de <<A HREF="http://online.de">http://online.de</A>> wrote: [q] > > Hello![/q] > [...] [q] > > I choosed the VHDL USART circuit from this forum and read the > > documentation. I was quite impressed about the complexity of[/q] > this [q] > > module and was unable to figure out how to just send some[/q] > single bytes [q] > > to my machine. > >[/q] > Maybe I overlooked one, but do you mean the > Serial UART > <A HREF="http://www.opencores.org/projects.cgi/web/uart">http://www.opencores.org/projects.cgi/web/uart</A>[/q] <<A HREF="http://www.opencores.org/projects.cgi/web/uart">http://www.opencores.org/projects.cgi/web/uart</A>> [q] > or the > UART 16550 > <A HREF="http://www.opencores.org/projects.cgi/web/uart16550">http://www.opencores.org/projects.cgi/web/uart16550</A> > The first one has a VHDL testbench, the later one only a Verilog > one. If > there is nothing in the documentation, the test bench might be the > best > place to look how they feed data into the core. > Cheers, > Guenter [q] > > Does someone have some lines of code that would give me a[/q] > start to [q] > > initialize this circuit? > > > > Many Thanks, > > Manue. > > _______________________________________________ > > <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> > >[/q] > >[/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> <<A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A>> ------------------------------------------------------------------------ _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A>[/q] most of the uarts on opencores come with tons of features hat you love if you got a cpu connected, if you just need a single baud-rate no fifo features no handshakes (or only cts/dts) you are better of looking at something as simple as http://direct.xilinx.com/bvdocs/appnotes/xapp341.pdf that gets communication up and running in a couple of hours. thilo Guy Hutchison wrote: This BSD page has some good information on the standard UART register set. In general your FPGA will need to have either a small microprocessor or a state machine to program the initial parameters into the UART and then push data into and out of it. Link: http://www.freebsd.org/doc/en_US.ISO8859-1/articles/serial-uart/article.html - Guy On 3/9/07, manuel.kampert at online.de manuel.kampert at online.de> manuel.kampert at online.de manuel.kampert at online.de>> wrote: The core that i've used was http://www.opencores.org/pdownloads.cgi/list/a_vhd_16550_uart Unfortunately it did not contain any testbench. ----- Original Message ----- From: GÃ¼nter Dannoritzerdannoritzer at w...> To: Date: Fri Mar 9 14:00:39 CET 2007 Subject: [oc] Serial / UART link to host > manuel.kampert at online.de http://online.de> wrote: > > Hello! > [...] > > I choosed the VHDL USART circuit from this forum and read the > > documentation. I was quite impressed about the complexity of > this > > module and was unable to figure out how to just send some > single bytes > > to my machine. > > > Maybe I overlooked one, but do you mean the > Serial UART > http://www.opencores.org/projects.cgi/web/uart http://www.opencores.org/projects.cgi/web/uart> > or the > UART 16550 > http://www.opencores.org/projects.cgi/web/uart16550 > The first one has a VHDL testbench, the later one only a Verilog > one. If > there is nothing in the documentation, the test bench might be the > best > place to look how they feed data into the core. > Cheers, > Guenter > > Does someone have some lines of code that would give me a > start to > > initialize this circuit? > > > > Many Thanks, > > Manue. > > _______________________________________________ > > http://www.opencores.org/mailman/listinfo/cores > > > > _______________________________________________ http://www.opencores.org/mailman/listinfo/cores http://www.opencores.org/mailman/listinfo/cores> ------------------------------------------------------------------------ _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

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