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I2C FPGA Inputs
by Unknown on Mar 19, 2007 |
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heedaf at excite.com wrote:
I’m not sure what “wb_adr_i†is for. Definition
Read the wishbone bus specification.
http://www.opencores.org/projects.cgi/web/wishbone/wishbone>
Regards,
--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
says it is “Lower address bits†but I’m not sure why this would be required. I’m also a little confused on “wb_we_i†and “wb_stb_i†and what their purpose is for. Please forgive me if these are dumb questions but I sure would appreciate the help. |
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I2C FPGA Inputs
by heedaf on Mar 19, 2007 |
heedaf
Posts: 7 Joined: Jun 23, 2008 Last seen: Aug 12, 2008 |
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IÂ’m new to the FPGA realm but IÂ’ve had a lot of experience with I2C and
microcontrollers so now I’m trying to learn the guts of I2C. On the I2C core listed on OpenCores can anyone give me a better definition of what the inputs are? I’m not sure what “wb_adr_i” is for. Definition says it is “Lower address bits” but I’m not sure why this would be required. I’m also a little confused on “wb_we_i” and “wb_stb_i” and what their purpose is for. Please forgive me if these are dumb questions but I sure would appreciate the help. |
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