Hi

I'm new to the cores world in my new work, but I know
something of VHDL. I was thinking to make a blinking led
and I thinked to make something like:

| Core |
| |
Led -- | PPort |
| |
| ROM | |
| RAM -|-> BlockRAM in VHDL

I have the C program but my boss asked me not to use all
AVR core because I will not use it all. He asked me to
delete some of the core block's like USART.

Can I simply delete the block in the schematic? I use HDL
Design of Mentor Graphics. What blocks do I need? Cor,
ROM, DataRAM and PPort. Do I need any more? because I want
the led blinking at 1s frequency maybe I need the wait,
but I don't know what I should or not delete from the
entire AVR Core.

Thank's in advance. I hope the little scheme help
Francisco Laranjeira

At 21:13 20/03/2007, you wrote:


It was ok. Just use a fixed width font for viewing

It seem's that the scheme was disconfigured. it's something like: ........._________.... ........|....Core....| ........|..............| leda21671 at a...> To: Date: Tue Mar 20 18:03:30 CET 2007 Subject: [oc] new to cores world, need a little help

Hase anyone tried using the I2C Core with XilinxÂ’s ISE? IÂ’ve found a problem with my project using this core. When I back trace the sci and scl outputs in the generated schematic they are not connected to ground. This would explain why the outputs arenÂ’t working. Any idea what may cause this problem? Thanks, DR _______________________________________________ Join Excite! - http://www.excite.com The most personalized portal on the Web! -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20070322/dc1e7247/attachment.htm

I believe I've found the problem. At the bottom of the "i2c_master_bit_ctrl.vhd,v 1.14 2006/10/11" scl and sda are assigned 0 and I can't find anywhere else that the they are updated. Has anyone come up with a fix for this?Thanks,DR -- assign outputs scl_o heedaf at excite.com > wrote:From: D R [mailto: heedaf at excite.com]To: cores at opencores.orgDate: Thu, 22 Mar 2007 14:05:13 -0400 (EDT)Subject: Re: [oc] new to cores world, need a little help Hase anyone tried using the I2C Core with XilinxÂ’s ISE? IÂ’ve found a problem with my project using this core. When I back trace the sci and scl outputs in the generated schematic they are not connected to ground. This would explain why the outputs arenÂ’t working. Any idea what may cause this problem? Thanks, DR Join Excite! - http://www.excite.comThe most personalized portal on the Web! _______________________________________________http://www.opencores.org/mailman/listinfo/cores _______________________________________________ Join Excite! - http://www.excite.com The most personalized portal on the Web! -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20070322/5cdc1820/attachment.htm

This is correct, the sci and scl signals are defined as open collector
(or open drain) outputs. You need to have external pullups to make
it work.

In verilog you can use the pullup/pulldown primitives. In VHDL I think you
have to have a weak driver in your testbench.

Clint

On Thu, 22 Mar 2007, D R wrote: