Hello, I'm working with the memory controller IP core to use a SDRAM from Rudolf Usselmann and have a little problem with the Cke signal. I have posted an image on my website to show the problem : http://xcsnake.free.fr/sdram_cke.png In my case, the write (we+cas+cs) signal is not taken by the SDRAM. This is because inside the RAM, the cke is late of 1 clock cycle (the signal without a name is the internal SDRAM clock signal). To correct this, the memory controller cke signal should be one clock cycle before. Is it a bug, or did I do something wrong ? Thank you Mickaël

In most cases CKE is activated upon initialization of the SDRAM and left that way. My best guess is that you started using the SDRAM before you initialized it. Erez. ----- Original Message ---- From: "xcsnake at free.fr" xcsnake at free.fr> To: cores at opencores.org Sent: Thursday, March 22, 2007 3:32:09 AM Subject: [oc] memory controller and Cke for SDRAM Hello, I'm working with the memory controller IP core to use a SDRAM from Rudolf Usselmann and have a little problem with the Cke signal. I have posted an image on my website to show the problem : http://xcsnake.free.fr/sdram_cke.png In my case, the write (we+cas+cs) signal is not taken by the SDRAM. This is because inside the RAM, the cke is late of 1 clock cycle (the signal without a name is the internal SDRAM clock signal). To correct this, the memory controller cke signal should be one clock cycle before. Is it a bug, or did I do something wrong ? Thank you Mickaël _______________________________________________ http://www.opencores.org/mailman/listinfo/cores -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20070321/615e3209/attachment.htm

No, the RAM is correctly initialized. Mickaël Selon Erez Birenzwig erez_birenzwig at yahoo.com>: