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Using Wishbone bus in Xilinx EDK
by Unknown on Mar 24, 2007 		Not available!
You need to design or find a bus bridge, e.g. OPB-to-Wishbone, or PLB-to-Wishbone. /Mikhail On Sat, 24 Mar 2007 02:58:20 +0100 (CET) Karim Ali khadgar34+opencores at gmail.com> wrote:
Hi, I am a beginner developer using XPS with one of the Xilinx Virtex 2 Pro FPGA. The board came with a baseline defined by the manufacturer, and it uses the Xilinx EDK (Xilinx Platform Studio). I'm wondering how would I use these open cores that have been developed with the Wishbone bus in mind. The Xilinx EDK only has the IBM CoreConnect busses for use it seems. I am currently trying to use the UART 16550 core on this site, and I don't know how to access it through the software in my projects. Any help is appreciated Karim _______________________________________________ http://www.opencores.org/mailman/listinfo/cores





Using Wishbone bus in Xilinx EDK
by Unknown on Mar 24, 2007 		Not available!
Hi,

I am a beginner developer using XPS with one of the Xilinx Virtex 2
Pro FPGA. The board came with a baseline defined by the manufacturer,
and it uses the Xilinx EDK (Xilinx Platform Studio).

I'm wondering how would I use these open cores that have been
developed with the Wishbone bus in mind. The Xilinx EDK only has the
IBM CoreConnect busses for use it seems.

I am currently trying to use the UART 16550 core on this site, and I
don't know how to access it through the software in my projects.

Any help is appreciated

Karim

no use no use 1/1 no use no use
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