I've got a core in vhdl that I've placed in a schematic. It has "wb_adr_i : in unsigned(2 downto 0); " for one of the pins and I have a marker connected to the bin via the schematic. When I try and simulate I'm getting the following errorERROR:Simulator:29 - at 0 ns : in I2C_Test(BEHAVIORAL), file (null): Default port map for entity Tri_State_Added to component Tri_State_Added connects std_logic_vector type local port wb_adr_i of the component to UNSIGNED type port of the entity.I believe the problem is that wb_adr_i is "unsigned" and the schematic pin connection is being treated as "std_logic_vector". Does anyone have any idea what the solution is?Thanks,DR _______________________________________________ Join Excite! - http://www.excite.com The most personalized portal on the Web! -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20070326/f163b8bd/attachment.htm

At the time the core was written it seemed a good idea to make the address
bus of type unsigned (it's an unsigned number after all).

You can simply replace the unsigned by std_logic_vector and see if that
solves your issue.

Richard