I'm still working on getting the I2C core working but I'm a little bit confused. It probably is simple but I can't figure it out. How do I implement the open drain and how is the line pulled to VCC? I've figured out how to do it in the schematic layout but I'm not sure on the VHDL side. How does the open-drain relate to the tri state buffer? Any help would be greatly appreciated. Thanks, DR _______________________________________________ Join Excite! - http://www.excite.com The most personalized portal on the Web! -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20070326/cf7193eb/attachment.htm

Please follow the guidelines in the documentation. There are graphical,
verilog, and vhdl examples.
Just copy and paste the code.


The line is pulled up to VCC by the external resistor.
The I2C bus implements a wired OR on it's lines.
In VHDL you have to simulate this in your testbench by driving SDA and SCL
to 'H'.


The tri-state implements the open drain.
Basically an open drain is capable of pulling a line low, but not high.
The same functionality is achieved by using a tri-state buffer that, when
enabled, pulls the line low.

scl assign scl = scl_oen ? 1'b0 : 1'bz.

Richard

On Mon, 26 Mar 2007 01:46:02 -0400 (EDT) "D R" heedaf at excite.com> wrote:

in VHDL:

output_pin
As someone has already mentioned, an external resistor is usally used
for the pullup. Most of the FPGAs have internal pullups you could try
using but they are usually too weak for I2C.

/Mikhail