Hello, I am trying to get a VHDL testbench running with the VHDL I2C core and and Verilog I2C slave model. I've implemented the WISHBONE master as a simple state machine. I tried to follow the same steps in the Verilog testbench in CVS but somehow that is insufficient. The I2C master drives the SCL and SDA lines from 'H' to '0' and '0' to 'H' as expected but the slave does not appear to respond to the commands. The slave SDA line is perpetually at 'Z'. At this point I am really not sure what might be wrong and am in desperate need of some help. The source files are available here: http://m.afgani.googlepages.com/WB_I2C.zip Thanks in advance, Mostafa

I've been working on this thing for weeks and I can't figure it out. Since you have some success, could I ask for your help with the verilog side? I'm using ISE 9.1 also, is there anyway that you would send me the verilog project and then maybe I can figure out what the heck I'm doing wrong. I'd sure appreciate it. If you can't, how did you add the test bench in the project? I put the "test_bench_top" on top of the "wb_master_model" all in one .v test benc file. I put the slave in its own .v file. Everything compiles correctly but the start command (8'h90) doesn't seem to be written. If I can get this running - then I'll try and give you a hand.Thanks,Dewayne--- On Mon 04/02, m.afgani at gmail.com > wrote:From: [mailto: m.afgani at gmail.com]To: cores at opencores.orgDate: Mon, 2 Apr 2007 10:58:17 +0200 (CEST)Subject: Re: [oc] I2C core VHDL testbenchHi,The verilog testbench works for me. That's why it's all the more frustrating. I am using Xilinx ISE 9.1.03iBest,MostafaPS> I'm copying this conversation to the OC forumOn 4/2/07, D R wrote:> > I've been trying to get either verilog or vhdl versions to work. I'm trying to the > verilog test bench to work but I'm getting similar errors. What software are you > using? I'm thinking that unless you use synopsis it won't work.----- Original Message ----- From: m.afgani at gmail.com To: Date: Mon Apr 2 02:18:49 CEST 2007 Subject: [oc] I2C core VHDL testbench > Hello, > > I am trying to get a VHDL testbench running with the VHDL I2C core > and > and Verilog I2C slave model. I've implemented the WISHBONE master > as a > simple state machine. I tried to follow the same steps in the > Verilog > testbench in CVS but somehow that is insufficient. The I2C master > drives the SCL and SDA lines from 'H' to '0' and '0' to 'H' as > expected but the slave does not appear to respond to the commands. > The > slave SDA line is perpetually at 'Z'. > At this point I am really not sure what might be wrong and am in > desperate need of some help. The source files are available here: > http://m.afgani.googlepages.com/WB_I2C.zip > Thanks in advance, > Mostafa > > _______________________________________________http://www.opencores.org/mailman/listinfo/cores _______________________________________________ Join Excite! - http://www.excite.com The most personalized portal on the Web! -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20070402/f7c70eee/attachment.htm

Hi, The verilog testbench works for me. That's why it's all the more frustrating. I am using Xilinx ISE 9.1.03i Best, Mostafa PS> I'm copying this conversation to the OC forum On 4/2/07, D R heedaf at excite.com> wrote: ----- Original Message ----- From: m.afgani at gmail.comm.afgani at g...> To: Date: Mon Apr 2 02:18:49 CEST 2007 Subject: [oc] I2C core VHDL testbench

The Verilog testbench is the one from CVS: ( i2c_slave_model.v, tst_bench_top.v, wb_master_model.v) http://www.opencores.org/cvsweb.shtml/i2c/bench/verilog/ (i2c_master_bit_ctrl.v, i2c_master_byte_ctrl.v, i2c_master_defines.v, i2c_master_top.v, timescale.v) http://www.opencores.org/cvsweb.shtml/i2c/rtl/verilog/ I simply created a new project and added all of those files. Then I ran a behavioral simulation of tst_bench_top.v using ISE simulator. -Mostafa ----- Original Message ----- From: D Rheedaf at e...> To: Date: Mon Apr 2 09:04:51 CEST 2007 Subject: [oc] I2C core VHDL testbench

hi mostafa,

Iam trying to do a similar project using i2c protocol...where i hav to
implement the master core using vhdl...
did u get successful results so that u can help me because i got struck
somewhere.....

Mostafa-3 wrote:
-- View this message in context: http://www.nabble.com/I2C-core-VHDL-testbench-tf3502675.html#a10002852 Sent from the OpenCores - IP Cores mailing list archive at Nabble.com.

Hi, There has been some previous debate regarding the 'H' versus '1' in VHDL. Consensus then was that an 'H' (weak/pull up high) inside a chip is a weird value. The pad or testbench should really convert 'H' into '1'. Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of m.afgani at gmail.com Sent: Friday, April 20, 2007 12:17 AM To: cores at opencores.org Subject: Re: [oc] I2C core VHDL testbench Hello, I've finally succeeded in creating a simple WISHBONE master and testbench in VHDL that seems to work with the VHDL I2C core (ISE Sim 9.1.03i). One major issue appears to be the fact the core cannot deal with SCL/SDA lines that toggle between 'H' and '0' -- requiring the use of the /to_X01()/ function for /scl_i/ and /sda_i/ in the testbench. Also, I chose to use a VHDL model for a 24Cxx I2C EEPROM rather than the verilog slave model in CVS. An archive with the contributed files can be found here: http://m.afgani.googlepages.com/wb_i2c_tb.zip I started working on this project a few weeks ago with no prior knowledge of any HDL. Therefore, the code is certain to be lacking in many respects. I would really appreciate it if some of the more experienced users would have a look and provide some feedback. Many thanks to Richard for the core. Regards, Mostafa _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Hello, I've finally succeeded in creating a simple WISHBONE master and testbench in VHDL that seems to work with the VHDL I2C core (ISE Sim 9.1.03i). One major issue appears to be the fact the core cannot deal with SCL/SDA lines that toggle between 'H' and '0' -- requiring the use of the /to_X01()/ function for /scl_i/ and /sda_i/ in the testbench. Also, I chose to use a VHDL model for a 24Cxx I2C EEPROM rather than the verilog slave model in CVS. An archive with the contributed files can be found here: http://m.afgani.googlepages.com/wb_i2c_tb.zip I started working on this project a few weeks ago with no prior knowledge of any HDL. Therefore, the code is certain to be lacking in many respects. I would really appreciate it if some of the more experienced users would have a look and provide some feedback. Many thanks to Richard for the core. Regards, Mostafa

Hi Richard, Thanks for the clarification. Perhaps you could add this information as a footnote in the docs or source preamble? As 'H' is a valid VHDL logic level, I initially did not consider it a problem -- resulting in time lost looking elsewhere =/ Best regards, Mostafa ----- Original Message ----- From: Richard Herveillerichard at h...> To: Date: Thu Apr 19 21:40:38 CEST 2007 Subject: [oc] I2C core VHDL testbench