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Available: Detailed RISC CPU IP Core Design Documentation
by Unknown on Apr 10, 2007 |
Not available! | ||
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Hello,
I have put up an article on our web site that describes a RISC CPU IP
Core
that was created for one of our clients:
http://www.summitsoftconsulting.com/Pic10IpCore.htm
The RISC IP Core is instruction-compatible with the Microchip
PIC10F200-series of microcontrollers. Full design documentation is
available
as well as full Verilog source code (including a full set of test
benches).
This is a generic Controller-Datapath design that easily can be ported
to VHDL.
Thanks,
/John.
--------------------------------------------
John Gulbrandsen, Summit Soft Consulting
Professional Windows Systems Programming
26895 Aliso Creek Rd. Suite B504
Aliso Viejo, CA 92656-5301
Phone (877) 839-2543
Fax (877) 349-1818
John.Gulbrandsen at SummitSoftConsulting.com
--------------------------------------------
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Available: Detailed RISC CPU IP Core Design Documentation
by Unknown on Apr 10, 2007 |
Not available! | ||
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John,
This looks like a neat little one. It is not the first PIC implementation I have seen out there, however, but this one does indeed seem to be very straight-forward and compact. Have you got any synthesis results on speed and area, e.g. how small does it get (to fit in a very small FPGA)? Does anyone know if there are legal issues in implementing one of the MicroChip PIC cores, i.e. is the instruction set not patented, or has it been placed into the public domain? I would expect MicroChip to have a commercial interest in defending their intellectual property, as they are making money on selling their standalone CPUs? /Peter
>Hello,
I have put up an article on our web site that describes a RISC CPU IP Core
that was created for one of our clients:
http://www.summitsoftconsulting.com/Pic10IpCore.htm
The RISC IP Core is instruction-compatible with the Microchip
PIC10F200-series of microcontrollers. Full design documentation is available
as well as full Verilog source code (including a full set of test benches).
This is a generic Controller-Datapath design that easily can be ported to VHDL.
Thanks,
/John.
---------------------------------
TV dinner still cooling?
Check out "Tonight's Picks" on Yahoo! TV.
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Available: Detailed RISC CPU IP Core Design Documentation
by Unknown on Apr 11, 2007 |
Not available! | ||
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Peter, you are right - the spec and implementation seems to be really nice, straight-forward and well documented. But if you have a second glance at it you'll realize that the available source code is not synthesizable - it's just a functional description... So I assume you'll have to buy the *real* core from SummitSoftConsulting - and that's why the description is posted here... Correct me if I'm wrong. Joern On Apr 10, 2007, at 2:55 PM, Peter Ulrik Mikkelsen wrote:
John,
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This looks like a neat little one. It is not the first PIC implementation I have seen out there, however, but this one does indeed seem to be very straight-forward and compact. Have you got any synthesis results on speed and area, e.g. how small does it get (to fit in a very small FPGA)? Does anyone know if there are legal issues in implementing one of the MicroChip PIC cores, i.e. is the instruction set not patented, or has it been placed into the public domain? I would expect MicroChip to have a commercial interest in defending their intellectual property, as they are making money on selling their standalone CPUs? /Peter
>Hello,
> >I have put up an article on our web site that describes a RISC CPU IP Core
>that was created for one of our clients:
>http://www.summitsoftconsulting.com/Pic10IpCore.htm
>
>The RISC IP Core is instruction-compatible with the Microchip
>PIC10F200-series of microcontrollers. Full design documentation is
available
>as well as full Verilog source code (including a full set of test
benches).
>This is a generic Controller-Datapath design that easily can be
ported to VHDL.
>
TV dinner still cooling?
Check out "Tonight's Picks" on Yahoo! TV.
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
>Thanks, >/John. |
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