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OpenRisc critical path
by Unknown on Dec 2, 2003 |
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Hey !
If you talk about OR1200 then the speed limit is indeed in the memory access
part (access to icache fetching new insn). The max clock frequency dpends
how you configure OR1200. With everything turned on (implemented) you can do
something like 125MHz on 0.18um worst case conditions. For example the
Flextronics chip runs in reality at 160MHz:
http://www.opencores.org/projects/or1k/Silicon
regards,
Damjan
----- Original Message -----
From: "Sylvain Aguirre" sylvain.aguirre@epfl.ch>
To: openrisc@opencores.org>
Sent: Monday, December 01, 2003 2:20 PM
Subject: [openrisc] OpenRisc critical path
Hi,
http://www.opencores.org/mailinglists.shtml
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I prepare a Ph.D in the microprocessor field and I would like to know what is the speed limitation of your processor. Is the memory access time a part of the critical path? And what speed can you reach in the worst case? Sylvain Aguirre. ==================================================================== Ph.D student STI-ITS-LTS3 Tel: +41-21-693-56-86 === Laboratoire de Systemes Integres 3 Fax: +41-21-693-46-63 === 1015 Lausanne, EPFL-Switzerland ==================================================================== -- To unsubscribe from openrisc mailing list please visit |
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