Dear All, I am a little confused about how I can use OpenRISC1K for my own project. Basically I am looking at a class of applications and want to 'customize' a core for that application set. By customize I want to possibly extend the instruction-set, add multi-threading support, customize memory architecture, customize register-sets, add co-processor and interfacing instructions. My final deliverable is a RTL implementation of my core. But I need to do simulations initially to judge the benefits of any 'customization' that I do. Right now I am not clear as to whether or not I can acheieve all this using Or1k. I have not looked into the simulator in detail..but was wondering what the feasibility is, hence my question on this mailing list. I am sure that the openrisc core was designed for such purposes. I will eventually have to write the RTL that's fine but is the simulator flexible enough for one to do the benefit analysis? Anyone else been through such a 'openRisc adaptation' process? Please let me know! LEARNER __________________________________ Do you Yahoo!? Find out what made the Top Yahoo! Searches of 2003 http://search.yahoo.com/top2003

What I would suggest is that you use a verilog simulator such as Icarus Verilog (look it up on sourceforge). Using verilog directives, it is possible to simulate a flash chip with Linux installed on it. You would have to run your processor for a while and see how well it handles the boot script and see how well it runs a testbench of applications (which you will also have to write). Measure the number of clocks used to complete the testbench. These might be very looooonnnnnnggggg sims. I don't know much about the simulator, but I am guessing that it will not be as flexible as you desire. This way you are measuring the RTL. If you have any questions, I can elaborate further. -Brian -----Original Message----- From: openrisc-bounces@opencores.org on behalf of kernel_learner Sent: Mon 1/5/2004 11:45 AM To: openrisc@opencores.org Cc: Subject: [openrisc] Using OpenRisc1000 Dear All, I am a little confused about how I can use OpenRISC1K for my own project. Basically I am looking at a class of applications and want to 'customize' a core for that application set. By customize I want to possibly extend the instruction-set, add multi-threading support, customize memory architecture, customize register-sets, add co-processor and interfacing instructions. My final deliverable is a RTL implementation of my core. But I need to do simulations initially to judge the benefits of any 'customization' that I do. Right now I am not clear as to whether or not I can acheieve all this using Or1k. I have not looked into the simulator in detail..but was wondering what the feasibility is, hence my question on this mailing list. I am sure that the openrisc core was designed for such purposes. I will eventually have to write the RTL that's fine but is the simulator flexible enough for one to do the benefit analysis? Anyone else been through such a 'openRisc adaptation' process? Please let me know! LEARNER __________________________________ Do you Yahoo!? Find out what made the Top Yahoo! Searches of 2003 http://search.yahoo.com/top2003 _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/ms-tnef Size: 3662 bytes Desc: not available Url : http://www.opencores.org/forums/openrisc/attachments/20040106/b5401f4d/attachment.bin