Hello all, I am new to openrisc so please be gentle. I guess I am still trying to figure about things about openrisc. I looked at the or1ksim and it seems like it is a functional simulator..but not a cycle-accurate simulator am I right? By that I mean it only cares for correctness but it cannot give me statistics like cache misses/hits no. of instructions executed or a dynamic instruction trace.. The manual on openrisc does not seem to be very specific in the architecture definition...I am wondering if that was done on purpose, i.e. to keep the definition loose..so my question is what is openRISC defining and what is it that it's not defining? I am also confused about the SMT support mentioned in the manual. Having multiple register contexts enables fast-switching but it does not mean it's SMT. It's SMT only if there is a fetch-logic which fetches from multiple threads and if multiple register-files are active simultaneously. Could someone please explain this to me in more detail? Also can I do fast-context-switching in the or1ksim...? Looking forward to replies.... Djorn --------------------------------- Do you Yahoo!? Yahoo! Hotjobs: Enter the "Signing Bonus" Sweepstakes -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums/openrisc/attachments/20040106/f563ecea/attachment.htm

Welcome Djorn!


right.


wrong. You can print these statistics out, but first you have to enable them
e.g. in sim.cfg


OpenRISC architecture is defining everything that is in the OpenRISC
architecture manual.


Why can't you? Each thread could have its own SR, with its own CID.


I suppose not, even if the code is inside, nobody has tested it, since there
is no implementation yet supporting this.

Best regards,

Marko

Hi Djorn, or1ksim is functuinal simulator or architectural simulator whatever term you prefer. It is not cycle accurate, but you don't need cycle accurate to have statistics of cache miss/hit. There is for example cache hit/miss statistics (you need to enable caches in your software code and use command "stats 1"). The simulator has some understanding of timing because you can set how fast your memories are (read cycle, write cycle) and you can also set how fast instructions can get executed however this is only to get a rough idea if you do performance analysis. The only time you need cycle accurate simulator if you want to know exact performance of a processor in order to squeeze an algorithm implementation that might run or might need more performance. However in most software development work cycle accuracy is not needed and only makes simulator to run slower. The definition is not perfect, however it is good enough to provide a platform for software development. Ie it describes software model in enough detail so that for some details you can have a look at a software port of an operating system to find any missing details. Of course in a perfect world you wouldn't have to do this. Also keep in mind that architecture manual is only architecture manual, it doesn't describe actual implementations (how fast instructions execute for example is a matter of implementation and not architecture etc). So if you have any contributions to the manual feel free to help us improve it. Fast context switching is separated from the SMT. The SMT would simply mean you have another fecther in your implementation. In fact there is not much reason why to describe SMT fetcher in architecture manual, this is a matter of implementation. The only thing a SMT is machine because it would need new sets of exception registers (EPCR, ESR etc). SMT and fast context switching is not implemented in orqksim or any implementation at the moment. regards, Damjan ----- Original Message ----- From: "rusky djorn" ruskydjorn@yahoo.com> To: openrisc@opencores.org> Sent: Tuesday, January 06, 2004 8:30 PM Subject: [openrisc] Questions regarding openrisc1000
figure about things about openrisc.

simulator..but not a cycle-accurate simulator am I right? By that I mean it
only cares for correctness but it cannot give me statistics like cache
misses/hits no. of instructions executed or a dynamic instruction trace..

architecture definition...I am wondering if that was done on purpose, i.e.
to keep the definition loose..so my question is what is openRISC defining
and what is it that it's not defining?

multiple register contexts enables fast-switching but it does not mean it's
SMT. It's SMT only if there is a fetch-logic which fetches from multiple
threads and if multiple register-files are

detail?



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Thank you very much for your useful replies. There are a few things more I need to understand..before I can start contributing in any way. 1. For my studies I really want to build an SMT - mutiple issue simulator. Has anyone started working on this or even thought about this, please give me some input. Also, I believe or1ksim is a single-issue simulator..I was tracking through the code and came across following functions which do the execute: decode_execute_wrapper() -> decode_execute() -> analysis(). They seem to be only issuing one instruction at a time. 2. Another question is about ucLinux..the web-page says it's an operating system for non-MMU microcontrollers i.e. uCs that use physical memory directly instead of virtual memory. In that case does the ucLinux port for or1k is for the case where there's no MMUs? I am confused about that. 3. Finally how easy or difficult would it be to extend the base ISA of openRisc? There's extra bits in the encoding which could be used to make new opcodes. If that's the case how do I add support for these new opcodes in the compiler/binutils? I guess I am just trying to analyze the feasibility of doing that...so I don't really want a detailed answer of how to do that...but just easy or difficult a task it is to addd new opcodes and their support in the compiler tools. I have more questions at this point than anything to contribute..but I am still on the learning curve. I liked the architecture of OpenRISC and I think it just provides people like me great opportunity to do something 'real' without worrying about licensing etc..:) Cheers! Djorn Damjan Lampret lampret@opencores.org> wrote: Hi Djorn, or1ksim is functuinal simulator or architectural simulator whatever term you prefer. It is not cycle accurate, but you don't need cycle accurate to have statistics of cache miss/hit. There is for example cache hit/miss statistics (you need to enable caches in your software code and use command "stats 1"). The simulator has some understanding of timing because you can set how fast your memories are (read cycle, write cycle) and you can also set how fast instructions can get executed however this is only to get a rough idea if you do performance analysis. The only time you need cycle accurate simulator if you want to know exact performance of a processor in order to squeeze an algorithm implementation that might run or might need more performance. However in most software development work cycle accuracy is not needed and only makes simulator to run slower. The definition is not perfect, however it is good enough to provide a platform for software development. Ie it describes software model in enough detail so that for some details you can have a look at a software port of an operating system to find any missing details. Of course in a perfect world you wouldn't have to do this. Also keep in mind that architecture manual is only architecture manual, it doesn't describe actual implementations (how fast instructions execute for example is a matter of implementation and not architecture etc). So if you have any contributions to the manual feel free to help us improve it. Fast context switching is separated from the SMT. The SMT would simply mean you have another fecther in your implementation. In fact there is not much reason why to describe SMT fetcher in architecture manual, this is a matter of implementation. The only thing a SMT is machine because it would need new sets of exception registers (EPCR, ESR etc). SMT and fast context switching is not implemented in orqksim or any implementation at the moment. regards, Damjan ----- Original Message ----- From: "rusky djorn" To: Sent: Tuesday, January 06, 2004 8:30 PM Subject: [openrisc] Questions regarding openrisc1000
figure about things about openrisc.

simulator..but not a cycle-accurate simulator am I right? By that I mean it
only cares for correctness but it cannot give me statistics like cache
misses/hits no. of instructions executed or a dynamic instruction trace..

architecture definition...I am wondering if that was done on purpose, i.e.
to keep the definition loose..so my question is what is openRISC defining
and what is it that it's not defining?

multiple register contexts enables fast-switching but it does not mean it's
SMT. It's SMT only if there is a fetch-logic which fetches from multiple
threads and if multiple register-files are

detail?



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