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OR1200 wishbone problem

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OR1200 wishbone problem by Unknown on Jan 9, 2004			Not available!
Hi Now OR1200 use wishbone interface.The handshake of wishbone cost at least one period,so it takes two clock periods to finish one instruction in average even using zero wait state rom.Now OR1200 execute one instruction in two period in average.So I think removing the wishbone handshake will improve the performence and will execute one instruction in one period in average.Is it possible to do that? Please correct me if I am wrong. Regards Hi Now OR1200 use wishbone interface.The handshake of wishbone cost at least one period,so it takes two clock periods to finish one instruction in average even using zero wait state rom.Now OR1200 execute one instruction in two period in average.So I think removing the wishbone handshake will improve the performence and will execute one instruction in one period in average.Is it possible to do that? Please correct me if I am wrong. Regards

OR1200 wishbone problem by Unknown on Jan 9, 2004			Not available!
Hi ! WB is used as on-chip interconnect bus. For max performance either use insn and data cache, or use embedded QMEM. If you use external RAM then performance is not optiomal. regards, Damjan ----- Original Message ----- From: <<A HREF="mailto:lzg@gddc.com.cn">lzg@gddc.com.cn</A>> To: <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> Sent: Friday, January 09, 2004 2:21 PM Subject: [openrisc] OR1200 wishbone problem [q] Hi Now OR1200 use wishbone interface.The handshake of wishbone cost at least one period,so it takes two clock periods to finish one instruction[/q] in [q] average even using zero wait state rom.Now OR1200 execute one instruction in two period in average.So I think removing the wishbone handshake will improve the performence and will execute one instruction in one period in average.Is it possible to do that? Please correct me if I am wrong. Regards _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A>[/q] Hi ! WB is used as on-chip interconnect bus. For max performance either use insn and data cache, or use embedded QMEM. If you use external RAM then performance is not optiomal. regards, Damjan ----- Original Message ----- From: lzg@gddc.com.cn> To: openrisc@opencores.org> Sent: Friday, January 09, 2004 2:21 PM Subject: [openrisc] OR1200 wishbone problem Hi Now OR1200 use wishbone interface.The handshake of wishbone cost at least one period,so it takes two clock periods to finish one instruction in average even using zero wait state rom.Now OR1200 execute one instruction in two period in average.So I think removing the wishbone handshake will improve the performence and will execute one instruction in one period in average.Is it possible to do that? Please correct me if I am wrong. Regards _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc

OR1200 wishbone problem by Unknown on Jan 9, 2004			Not available!
Hi I use WB to connect embedded QMEM as insn rom. But it also takes two clock periods to finish one instruction in the RTL simulation. Regards ----- Original Message ----- From: "Damjan Lampret" <<A HREF="mailto:lampret@opencores.org">lampret@opencores.org</A>> To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> Sent: Friday, January 09, 2004 10:02 PM Subject: Re: [openrisc] OR1200 wishbone problem [q] Hi ! WB is used as on-chip interconnect bus. For max performance either use insn and data cache, or use embedded QMEM. If you use external RAM then performance is not optiomal. regards, Damjan ----- Original Message ----- From: <<A HREF="mailto:lzg@gddc.com.cn">lzg@gddc.com.cn</A>> To: <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> Sent: Friday, January 09, 2004 2:21 PM Subject: [openrisc] OR1200 wishbone problem [q]> Hi > Now OR1200 use wishbone interface.The handshake of wishbone cost at > least one period,so it takes two clock periods to finish one instruction[/q] in [q]> average even using zero wait state rom.Now OR1200 execute one > instruction in two period in average.So I think removing the wishbone > handshake will improve the performence and will execute one instruction > in one period in average.Is it possible to do that? > Please correct me if I am wrong. > > Regards > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A>[/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> [/q] Hi I use WB to connect embedded QMEM as insn rom. But it also takes two clock periods to finish one instruction in the RTL simulation. Regards ----- Original Message ----- From: "Damjan Lampret" lampret@opencores.org> To: "List about OpenRISC project" openrisc@opencores.org> Sent: Friday, January 09, 2004 10:02 PM Subject: Re: [openrisc] OR1200 wishbone problem Hi ! WB is used as on-chip interconnect bus. For max performance either use insn and data cache, or use embedded QMEM. If you use external RAM then performance is not optiomal. regards, Damjan ----- Original Message ----- From: lzg@gddc.com.cn> To: openrisc@opencores.org> Sent: Friday, January 09, 2004 2:21 PM Subject: [openrisc] OR1200 wishbone problem > Hi > Now OR1200 use wishbone interface.The handshake of wishbone cost at > least one period,so it takes two clock periods to finish one instruction in > average even using zero wait state rom.Now OR1200 execute one > instruction in two period in average.So I think removing the wishbone > handshake will improve the performence and will execute one instruction > in one period in average.Is it possible to do that? > Please correct me if I am wrong. > > Regards > _______________________________________________ > http://www.opencores.org/mailman/listinfo/openrisc _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc

OR1200 wishbone problem by Unknown on Jan 9, 2004			Not available!
Hi ! QMEM doesn't use WB. QMEM is inside OR1200. Make sure you download or1200 from branch branch_qmem! regards, Damjan ----- Original Message ----- From: "Liu Zhigang" <<A HREF="mailto:305liuzg@163.net">305liuzg@163.net</A>> To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> Sent: Friday, January 09, 2004 4:32 PM Subject: Re: [openrisc] OR1200 wishbone problem [q] Hi I use WB to connect embedded QMEM as insn rom. But it also takes two clock periods to finish one instruction in the RTL[/q] simulation. [q] Regards ----- Original Message ----- From: "Damjan Lampret" <<A HREF="mailto:lampret@opencores.org">lampret@opencores.org</A>> To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> Sent: Friday, January 09, 2004 10:02 PM Subject: Re: [openrisc] OR1200 wishbone problem [q]> Hi ! > > WB is used as on-chip interconnect bus. For max performance either use[/q] insn [q]> and data cache, or use embedded QMEM. If you use external RAM then > performance is not optiomal. > > regards, > Damjan > > ----- Original Message ----- > From: <<A HREF="mailto:lzg@gddc.com.cn">lzg@gddc.com.cn</A>> > To: <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > Sent: Friday, January 09, 2004 2:21 PM > Subject: [openrisc] OR1200 wishbone problem > > [q] > Hi > Now OR1200 use wishbone interface.The handshake of wishbone cost at > least one period,so it takes two clock periods to finish one[/q] instruction [q]> in [q] > average even using zero wait state rom.Now OR1200 execute one > instruction in two period in average.So I think removing the wishbone > handshake will improve the performence and will execute one[/q] instruction [q] > in one period in average.Is it possible to do that? > Please correct me if I am wrong. > > Regards > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A>[/q] > > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> > >[/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A>[/q] Hi ! QMEM doesn't use WB. QMEM is inside OR1200. Make sure you download or1200 from branch branch_qmem! regards, Damjan ----- Original Message ----- From: "Liu Zhigang" 305liuzg@163.net> To: "List about OpenRISC project" openrisc@opencores.org> Sent: Friday, January 09, 2004 4:32 PM Subject: Re: [openrisc] OR1200 wishbone problem Hi I use WB to connect embedded QMEM as insn rom. But it also takes two clock periods to finish one instruction in the RTL simulation. Regards ----- Original Message ----- From: "Damjan Lampret" lampret@opencores.org> To: "List about OpenRISC project" openrisc@opencores.org> Sent: Friday, January 09, 2004 10:02 PM Subject: Re: [openrisc] OR1200 wishbone problem > Hi ! > > WB is used as on-chip interconnect bus. For max performance either use insn > and data cache, or use embedded QMEM. If you use external RAM then > performance is not optiomal. > > regards, > Damjan > > ----- Original Message ----- > From: lzg@gddc.com.cn> > To: openrisc@opencores.org> > Sent: Friday, January 09, 2004 2:21 PM > Subject: [openrisc] OR1200 wishbone problem > > > Hi > Now OR1200 use wishbone interface.The handshake of wishbone cost at > least one period,so it takes two clock periods to finish one instruction > in > average even using zero wait state rom.Now OR1200 execute one > instruction in two period in average.So I think removing the wishbone > handshake will improve the performence and will execute one instruction > in one period in average.Is it possible to do that? > Please correct me if I am wrong. > > Regards > _______________________________________________ > http://www.opencores.org/mailman/listinfo/openrisc > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/openrisc > > _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc

OR1200 wishbone problem by Unknown on Jan 9, 2004			Not available!
Hi Damjan Is It possible to the special memory using WB to make instruction execution with 0 wait state? And then it can takes only one clock periods to finish one instruction! Regards ----- Original Message ----- From: "Damjan Lampret" <<A HREF="mailto:lampret@opencores.org">lampret@opencores.org</A>> To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> Sent: Friday, January 09, 2004 11:40 PM Subject: Re: [openrisc] OR1200 wishbone problem [q] Hi ! QMEM doesn't use WB. QMEM is inside OR1200. Make sure you download or1200 from branch branch_qmem! regards, Damjan ----- Original Message ----- From: "Liu Zhigang" <<A HREF="mailto:305liuzg@163.net">305liuzg@163.net</A>> To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> Sent: Friday, January 09, 2004 4:32 PM Subject: Re: [openrisc] OR1200 wishbone problem [q]> Hi > I use WB to connect embedded QMEM as insn rom. > But it also takes two clock periods to finish one instruction in the RTL[/q] simulation. [q]> > Regards > > > ----- Original Message ----- > From: "Damjan Lampret" <<A HREF="mailto:lampret@opencores.org">lampret@opencores.org</A>> > To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > Sent: Friday, January 09, 2004 10:02 PM > Subject: Re: [openrisc] OR1200 wishbone problem > > [q] > Hi ! > > WB is used as on-chip interconnect bus. For max performance either use[/q] insn [q] > and data cache, or use embedded QMEM. If you use external RAM then > performance is not optiomal. > > regards, > Damjan > > ----- Original Message ----- > From: <<A HREF="mailto:lzg@gddc.com.cn">lzg@gddc.com.cn</A>> > To: <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > Sent: Friday, January 09, 2004 2:21 PM > Subject: [openrisc] OR1200 wishbone problem > > [q]> > Hi > > Now OR1200 use wishbone interface.The handshake of wishbone cost at > > least one period,so it takes two clock periods to finish one[/q] instruction [q] > in [q]> > average even using zero wait state rom.Now OR1200 execute one > > instruction in two period in average.So I think removing the wishbone > > handshake will improve the performence and will execute one[/q] instruction [q]> > in one period in average.Is it possible to do that? > > Please correct me if I am wrong. > > > > Regards > > _______________________________________________ > > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A>[/q] > > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> > >[/q] > > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A>[/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> [/q] Hi Damjan Is It possible to the special memory using WB to make instruction execution with 0 wait state? And then it can takes only one clock periods to finish one instruction! Regards ----- Original Message ----- From: "Damjan Lampret" lampret@opencores.org> To: "List about OpenRISC project" openrisc@opencores.org> Sent: Friday, January 09, 2004 11:40 PM Subject: Re: [openrisc] OR1200 wishbone problem Hi ! QMEM doesn't use WB. QMEM is inside OR1200. Make sure you download or1200 from branch branch_qmem! regards, Damjan ----- Original Message ----- From: "Liu Zhigang" 305liuzg@163.net> To: "List about OpenRISC project" openrisc@opencores.org> Sent: Friday, January 09, 2004 4:32 PM Subject: Re: [openrisc] OR1200 wishbone problem > Hi > I use WB to connect embedded QMEM as insn rom. > But it also takes two clock periods to finish one instruction in the RTL simulation. > > Regards > > > ----- Original Message ----- > From: "Damjan Lampret" lampret@opencores.org> > To: "List about OpenRISC project" openrisc@opencores.org> > Sent: Friday, January 09, 2004 10:02 PM > Subject: Re: [openrisc] OR1200 wishbone problem > > > Hi ! > > WB is used as on-chip interconnect bus. For max performance either use insn > and data cache, or use embedded QMEM. If you use external RAM then > performance is not optiomal. > > regards, > Damjan > > ----- Original Message ----- > From: lzg@gddc.com.cn> > To: openrisc@opencores.org> > Sent: Friday, January 09, 2004 2:21 PM > Subject: [openrisc] OR1200 wishbone problem > > > > Hi > > Now OR1200 use wishbone interface.The handshake of wishbone cost at > > least one period,so it takes two clock periods to finish one instruction > in > > average even using zero wait state rom.Now OR1200 execute one > > instruction in two period in average.So I think removing the wishbone > > handshake will improve the performence and will execute one instruction > > in one period in average.Is it possible to do that? > > Please correct me if I am wrong. > > > > Regards > > _______________________________________________ > > http://www.opencores.org/mailman/listinfo/openrisc > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/openrisc > > > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/openrisc _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc

OR1200 wishbone problem by Unknown on Jan 9, 2004			Not available!
Hi ! Not with WB. But there is QMEM integrated in the OR1200 exactly for this purpose. To have RISC w/o caches but with fixed memory (ROM or RAM) being able to execute insns 1 per clock cycle. Look at or1200_defines.v if you have define OR1200_QMEM_IMPLEMENTED enabled. Then just instantiate your ROM/RAM from your library in file or1200_qmem_top.v (instance name in current file is or1200_qmem_ram). If you don't have or1200_qmem_top.v file then you don't have branch_qmem branch of the OR1200 sources and you should download them !! regards, Damjan ----- Original Message ----- From: "Liu Zhigang" <<A HREF="mailto:305liuzg@163.net">305liuzg@163.net</A>> To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> Sent: Friday, January 09, 2004 6:03 PM Subject: Re: [openrisc] OR1200 wishbone problem [q] Hi Damjan Is It possible to the special memory using WB to make instruction execution with 0 wait state? And then it can takes only one clock periods to finish one instruction! Regards ----- Original Message ----- From: "Damjan Lampret" <<A HREF="mailto:lampret@opencores.org">lampret@opencores.org</A>> To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> Sent: Friday, January 09, 2004 11:40 PM Subject: Re: [openrisc] OR1200 wishbone problem [q]> Hi ! > > QMEM doesn't use WB. QMEM is inside OR1200. Make sure you download[/q] or1200 [q]> from branch branch_qmem! > > regards, > Damjan > > ----- Original Message ----- > From: "Liu Zhigang" <<A HREF="mailto:305liuzg@163.net">305liuzg@163.net</A>> > To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > Sent: Friday, January 09, 2004 4:32 PM > Subject: Re: [openrisc] OR1200 wishbone problem > > [q] > Hi > I use WB to connect embedded QMEM as insn rom. > But it also takes two clock periods to finish one instruction in the[/q] RTL [q]> simulation. [q] > > Regards > > > ----- Original Message ----- > From: "Damjan Lampret" <<A HREF="mailto:lampret@opencores.org">lampret@opencores.org</A>> > To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > Sent: Friday, January 09, 2004 10:02 PM > Subject: Re: [openrisc] OR1200 wishbone problem > > [q]> > Hi ! > > > > WB is used as on-chip interconnect bus. For max performance either[/q] use [q]> insn [q]> > and data cache, or use embedded QMEM. If you use external RAM then > > performance is not optiomal. > > > > regards, > > Damjan > > > > ----- Original Message ----- > > From: <<A HREF="mailto:lzg@gddc.com.cn">lzg@gddc.com.cn</A>> > > To: <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > > Sent: Friday, January 09, 2004 2:21 PM > > Subject: [openrisc] OR1200 wishbone problem > > > > [q] > > Hi > > Now OR1200 use wishbone interface.The handshake of wishbone cost[/q] at [q] > > least one period,so it takes two clock periods to finish one[/q] > instruction [q]> > in [q] > > average even using zero wait state rom.Now OR1200 execute one > > instruction in two period in average.So I think removing the[/q] wishbone [q] > > handshake will improve the performence and will execute one[/q] > instruction [q] > > in one period in average.Is it possible to do that? > > Please correct me if I am wrong. > > > > Regards > > _______________________________________________ > > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A>[/q] > > > > _______________________________________________ > > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> > > > >[/q] > > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A>[/q] > > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> >[/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A>[/q] Hi ! Not with WB. But there is QMEM integrated in the OR1200 exactly for this purpose. To have RISC w/o caches but with fixed memory (ROM or RAM) being able to execute insns 1 per clock cycle. Look at or1200_defines.v if you have define OR1200_QMEM_IMPLEMENTED enabled. Then just instantiate your ROM/RAM from your library in file or1200_qmem_top.v (instance name in current file is or1200_qmem_ram). If you don't have or1200_qmem_top.v file then you don't have branch_qmem branch of the OR1200 sources and you should download them !! regards, Damjan ----- Original Message ----- From: "Liu Zhigang" 305liuzg@163.net> To: "List about OpenRISC project" openrisc@opencores.org> Sent: Friday, January 09, 2004 6:03 PM Subject: Re: [openrisc] OR1200 wishbone problem Hi Damjan Is It possible to the special memory using WB to make instruction execution with 0 wait state? And then it can takes only one clock periods to finish one instruction! Regards ----- Original Message ----- From: "Damjan Lampret" lampret@opencores.org> To: "List about OpenRISC project" openrisc@opencores.org> Sent: Friday, January 09, 2004 11:40 PM Subject: Re: [openrisc] OR1200 wishbone problem > Hi ! > > QMEM doesn't use WB. QMEM is inside OR1200. Make sure you download or1200 > from branch branch_qmem! > > regards, > Damjan > > ----- Original Message ----- > From: "Liu Zhigang" 305liuzg@163.net> > To: "List about OpenRISC project" openrisc@opencores.org> > Sent: Friday, January 09, 2004 4:32 PM > Subject: Re: [openrisc] OR1200 wishbone problem > > > Hi > I use WB to connect embedded QMEM as insn rom. > But it also takes two clock periods to finish one instruction in the RTL > simulation. > > Regards > > > ----- Original Message ----- > From: "Damjan Lampret" lampret@opencores.org> > To: "List about OpenRISC project" openrisc@opencores.org> > Sent: Friday, January 09, 2004 10:02 PM > Subject: Re: [openrisc] OR1200 wishbone problem > > > > Hi ! > > > > WB is used as on-chip interconnect bus. For max performance either use > insn > > and data cache, or use embedded QMEM. If you use external RAM then > > performance is not optiomal. > > > > regards, > > Damjan > > > > ----- Original Message ----- > > From: lzg@gddc.com.cn> > > To: openrisc@opencores.org> > > Sent: Friday, January 09, 2004 2:21 PM > > Subject: [openrisc] OR1200 wishbone problem > > > > > > Hi > > Now OR1200 use wishbone interface.The handshake of wishbone cost at > > least one period,so it takes two clock periods to finish one > instruction > > in > > average even using zero wait state rom.Now OR1200 execute one > > instruction in two period in average.So I think removing the wishbone > > handshake will improve the performence and will execute one > instruction > > in one period in average.Is it possible to do that? > > Please correct me if I am wrong. > > > > Regards > > _______________________________________________ > > http://www.opencores.org/mailman/listinfo/openrisc > > > > _______________________________________________ > > http://www.opencores.org/mailman/listinfo/openrisc > > > > > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/openrisc > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/openrisc > _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc

OR1200 wishbone problem by Unknown on Jan 10, 2004			Not available!
Hi Damjan Thanks very much.I will try it. It will be helpful! Regards ----- Original Message ----- From: "Damjan Lampret" <<A HREF="mailto:lampret@opencores.org">lampret@opencores.org</A>> To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> Sent: Saturday, January 10, 2004 1:15 AM Subject: Re: [openrisc] OR1200 wishbone problem [q] Hi ! Not with WB. But there is QMEM integrated in the OR1200 exactly for this purpose. To have RISC w/o caches but with fixed memory (ROM or RAM) being able to execute insns 1 per clock cycle. Look at or1200_defines.v if you have define OR1200_QMEM_IMPLEMENTED enabled. Then just instantiate your ROM/RAM from your library in file or1200_qmem_top.v (instance name in current file is or1200_qmem_ram). If you don't have or1200_qmem_top.v file then you don't have branch_qmem branch of the OR1200 sources and you should download them !! regards, Damjan ----- Original Message ----- From: "Liu Zhigang" <<A HREF="mailto:305liuzg@163.net">305liuzg@163.net</A>> To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> Sent: Friday, January 09, 2004 6:03 PM Subject: Re: [openrisc] OR1200 wishbone problem [q]> Hi Damjan > Is It possible to the special memory using WB to make > instruction execution with 0 wait state? > And then it can takes only one clock periods to finish one instruction! > > Regards > > ----- Original Message ----- > From: "Damjan Lampret" <<A HREF="mailto:lampret@opencores.org">lampret@opencores.org</A>> > To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > Sent: Friday, January 09, 2004 11:40 PM > Subject: Re: [openrisc] OR1200 wishbone problem > > [q] > Hi ! > > QMEM doesn't use WB. QMEM is inside OR1200. Make sure you download[/q] or1200 [q] > from branch branch_qmem! > > regards, > Damjan > > ----- Original Message ----- > From: "Liu Zhigang" <<A HREF="mailto:305liuzg@163.net">305liuzg@163.net</A>> > To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > Sent: Friday, January 09, 2004 4:32 PM > Subject: Re: [openrisc] OR1200 wishbone problem > > [q]> > Hi > > I use WB to connect embedded QMEM as insn rom. > > But it also takes two clock periods to finish one instruction in the[/q] RTL [q] > simulation. [q]> > > > Regards > > > > > > ----- Original Message ----- > > From: "Damjan Lampret" <<A HREF="mailto:lampret@opencores.org">lampret@opencores.org</A>> > > To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > > Sent: Friday, January 09, 2004 10:02 PM > > Subject: Re: [openrisc] OR1200 wishbone problem > > > > [q] > > Hi ! > > > > WB is used as on-chip interconnect bus. For max performance either[/q] use [q] > insn [q] > > and data cache, or use embedded QMEM. If you use external RAM then > > performance is not optiomal. > > > > regards, > > Damjan > > > > ----- Original Message ----- > > From: <<A HREF="mailto:lzg@gddc.com.cn">lzg@gddc.com.cn</A>> > > To: <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > > Sent: Friday, January 09, 2004 2:21 PM > > Subject: [openrisc] OR1200 wishbone problem > > > > [q]> > > Hi > > > Now OR1200 use wishbone interface.The handshake of wishbone cost[/q] at [q]> > > least one period,so it takes two clock periods to finish one[/q] > instruction [q] > > in [q]> > > average even using zero wait state rom.Now OR1200 execute one > > > instruction in two period in average.So I think removing the[/q] wishbone [q]> > > handshake will improve the performence and will execute one[/q] > instruction [q]> > > in one period in average.Is it possible to do that? > > > Please correct me if I am wrong. > > > > > > Regards > > > _______________________________________________ > > > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A>[/q] > > > > _______________________________________________ > > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> > > > >[/q] > > > > _______________________________________________ > > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A>[/q] > > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> >[/q] > > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A>[/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> [/q] Hi Damjan Thanks very much.I will try it. It will be helpful! Regards ----- Original Message ----- From: "Damjan Lampret" lampret@opencores.org> To: "List about OpenRISC project" openrisc@opencores.org> Sent: Saturday, January 10, 2004 1:15 AM Subject: Re: [openrisc] OR1200 wishbone problem Hi ! Not with WB. But there is QMEM integrated in the OR1200 exactly for this purpose. To have RISC w/o caches but with fixed memory (ROM or RAM) being able to execute insns 1 per clock cycle. Look at or1200_defines.v if you have define OR1200_QMEM_IMPLEMENTED enabled. Then just instantiate your ROM/RAM from your library in file or1200_qmem_top.v (instance name in current file is or1200_qmem_ram). If you don't have or1200_qmem_top.v file then you don't have branch_qmem branch of the OR1200 sources and you should download them !! regards, Damjan ----- Original Message ----- From: "Liu Zhigang" 305liuzg@163.net> To: "List about OpenRISC project" openrisc@opencores.org> Sent: Friday, January 09, 2004 6:03 PM Subject: Re: [openrisc] OR1200 wishbone problem > Hi Damjan > Is It possible to the special memory using WB to make > instruction execution with 0 wait state? > And then it can takes only one clock periods to finish one instruction! > > Regards > > ----- Original Message ----- > From: "Damjan Lampret" lampret@opencores.org> > To: "List about OpenRISC project" openrisc@opencores.org> > Sent: Friday, January 09, 2004 11:40 PM > Subject: Re: [openrisc] OR1200 wishbone problem > > > Hi ! > > QMEM doesn't use WB. QMEM is inside OR1200. Make sure you download or1200 > from branch branch_qmem! > > regards, > Damjan > > ----- Original Message ----- > From: "Liu Zhigang" 305liuzg@163.net> > To: "List about OpenRISC project" openrisc@opencores.org> > Sent: Friday, January 09, 2004 4:32 PM > Subject: Re: [openrisc] OR1200 wishbone problem > > > > Hi > > I use WB to connect embedded QMEM as insn rom. > > But it also takes two clock periods to finish one instruction in the RTL > simulation. > > > > Regards > > > > > > ----- Original Message ----- > > From: "Damjan Lampret" lampret@opencores.org> > > To: "List about OpenRISC project" openrisc@opencores.org> > > Sent: Friday, January 09, 2004 10:02 PM > > Subject: Re: [openrisc] OR1200 wishbone problem > > > > > > Hi ! > > > > WB is used as on-chip interconnect bus. For max performance either use > insn > > and data cache, or use embedded QMEM. If you use external RAM then > > performance is not optiomal. > > > > regards, > > Damjan > > > > ----- Original Message ----- > > From: lzg@gddc.com.cn> > > To: openrisc@opencores.org> > > Sent: Friday, January 09, 2004 2:21 PM > > Subject: [openrisc] OR1200 wishbone problem > > > > > > > Hi > > > Now OR1200 use wishbone interface.The handshake of wishbone cost at > > > least one period,so it takes two clock periods to finish one > instruction > > in > > > average even using zero wait state rom.Now OR1200 execute one > > > instruction in two period in average.So I think removing the wishbone > > > handshake will improve the performence and will execute one > instruction > > > in one period in average.Is it possible to do that? > > > Please correct me if I am wrong. > > > > > > Regards > > > _______________________________________________ > > > http://www.opencores.org/mailman/listinfo/openrisc > > > > _______________________________________________ > > http://www.opencores.org/mailman/listinfo/openrisc > > > > > > > > _______________________________________________ > > http://www.opencores.org/mailman/listinfo/openrisc > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/openrisc > > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/openrisc _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc

OR1200 wishbone problem by Unknown on Jan 10, 2004			Not available!
----- Original Message ----- From: "Damjan Lampret" <<A HREF="mailto:lampret@opencores.org">lampret@opencores.org</A>> To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> Sent: Saturday, January 10, 2004 1:15 AM Subject: Re: [openrisc] OR1200 wishbone problem [q] Hi ! Not with WB. But there is QMEM integrated in the OR1200 exactly for this purpose. To have RISC w/o caches but with fixed memory (ROM or RAM) being able to execute insns 1 per clock cycle. Look at or1200_defines.v if you have define OR1200_QMEM_IMPLEMENTED enabled. Then just instantiate your ROM/RAM from your library in file or1200_qmem_top.v (instance name in current file is or1200_qmem_ram). If you don't have or1200_qmem_top.v file then you don't have branch_qmem branch of the OR1200 sources and you should download them !! regards, Damjan ----- Original Message ----- From: "Liu Zhigang" <<A HREF="mailto:305liuzg@163.net">305liuzg@163.net</A>> To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> Sent: Friday, January 09, 2004 6:03 PM Subject: Re: [openrisc] OR1200 wishbone problem [q]> Hi Damjan > Is It possible to the special memory using WB to make > instruction execution with 0 wait state? > And then it can takes only one clock periods to finish one instruction! > > Regards > > ----- Original Message ----- > From: "Damjan Lampret" <<A HREF="mailto:lampret@opencores.org">lampret@opencores.org</A>> > To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > Sent: Friday, January 09, 2004 11:40 PM > Subject: Re: [openrisc] OR1200 wishbone problem > > [q] > Hi ! > > QMEM doesn't use WB. QMEM is inside OR1200. Make sure you download[/q] or1200 [q] > from branch branch_qmem! > > regards, > Damjan > > ----- Original Message ----- > From: "Liu Zhigang" <<A HREF="mailto:305liuzg@163.net">305liuzg@163.net</A>> > To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > Sent: Friday, January 09, 2004 4:32 PM > Subject: Re: [openrisc] OR1200 wishbone problem > > [q]> > Hi > > I use WB to connect embedded QMEM as insn rom. > > But it also takes two clock periods to finish one instruction in the[/q] RTL [q] > simulation. [q]> > > > Regards > > > > > > ----- Original Message ----- > > From: "Damjan Lampret" <<A HREF="mailto:lampret@opencores.org">lampret@opencores.org</A>> > > To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > > Sent: Friday, January 09, 2004 10:02 PM > > Subject: Re: [openrisc] OR1200 wishbone problem > > > > [q] > > Hi ! > > > > WB is used as on-chip interconnect bus. For max performance either[/q] use [q] > insn [q] > > and data cache, or use embedded QMEM. If you use external RAM then > > performance is not optiomal. > > > > regards, > > Damjan > > > > ----- Original Message ----- > > From: <<A HREF="mailto:lzg@gddc.com.cn">lzg@gddc.com.cn</A>> > > To: <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > > Sent: Friday, January 09, 2004 2:21 PM > > Subject: [openrisc] OR1200 wishbone problem > > > > [q]> > > Hi > > > Now OR1200 use wishbone interface.The handshake of wishbone cost[/q] at [q]> > > least one period,so it takes two clock periods to finish one[/q] > instruction [q] > > in [q]> > > average even using zero wait state rom.Now OR1200 execute one > > > instruction in two period in average.So I think removing the[/q] wishbone [q]> > > handshake will improve the performence and will execute one[/q] > instruction [q]> > > in one period in average.Is it possible to do that? > > > Please correct me if I am wrong. > > > > > > Regards > > > _______________________________________________ > > > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A>[/q] > > > > _______________________________________________ > > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> > > > >[/q] > > > > _______________________________________________ > > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A>[/q] > > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> >[/q] > > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A>[/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> [/q] ----- Original Message ----- From: "Damjan Lampret" lampret@opencores.org> To: "List about OpenRISC project" openrisc@opencores.org> Sent: Saturday, January 10, 2004 1:15 AM Subject: Re: [openrisc] OR1200 wishbone problem Hi ! Not with WB. But there is QMEM integrated in the OR1200 exactly for this purpose. To have RISC w/o caches but with fixed memory (ROM or RAM) being able to execute insns 1 per clock cycle. Look at or1200_defines.v if you have define OR1200_QMEM_IMPLEMENTED enabled. Then just instantiate your ROM/RAM from your library in file or1200_qmem_top.v (instance name in current file is or1200_qmem_ram). If you don't have or1200_qmem_top.v file then you don't have branch_qmem branch of the OR1200 sources and you should download them !! regards, Damjan ----- Original Message ----- From: "Liu Zhigang" 305liuzg@163.net> To: "List about OpenRISC project" openrisc@opencores.org> Sent: Friday, January 09, 2004 6:03 PM Subject: Re: [openrisc] OR1200 wishbone problem > Hi Damjan > Is It possible to the special memory using WB to make > instruction execution with 0 wait state? > And then it can takes only one clock periods to finish one instruction! > > Regards > > ----- Original Message ----- > From: "Damjan Lampret" lampret@opencores.org> > To: "List about OpenRISC project" openrisc@opencores.org> > Sent: Friday, January 09, 2004 11:40 PM > Subject: Re: [openrisc] OR1200 wishbone problem > > > Hi ! > > QMEM doesn't use WB. QMEM is inside OR1200. Make sure you download or1200 > from branch branch_qmem! > > regards, > Damjan > > ----- Original Message ----- > From: "Liu Zhigang" 305liuzg@163.net> > To: "List about OpenRISC project" openrisc@opencores.org> > Sent: Friday, January 09, 2004 4:32 PM > Subject: Re: [openrisc] OR1200 wishbone problem > > > > Hi > > I use WB to connect embedded QMEM as insn rom. > > But it also takes two clock periods to finish one instruction in the RTL > simulation. > > > > Regards > > > > > > ----- Original Message ----- > > From: "Damjan Lampret" lampret@opencores.org> > > To: "List about OpenRISC project" openrisc@opencores.org> > > Sent: Friday, January 09, 2004 10:02 PM > > Subject: Re: [openrisc] OR1200 wishbone problem > > > > > > Hi ! > > > > WB is used as on-chip interconnect bus. For max performance either use > insn > > and data cache, or use embedded QMEM. If you use external RAM then > > performance is not optiomal. > > > > regards, > > Damjan > > > > ----- Original Message ----- > > From: lzg@gddc.com.cn> > > To: openrisc@opencores.org> > > Sent: Friday, January 09, 2004 2:21 PM > > Subject: [openrisc] OR1200 wishbone problem > > > > > > > Hi > > > Now OR1200 use wishbone interface.The handshake of wishbone cost at > > > least one period,so it takes two clock periods to finish one > instruction > > in > > > average even using zero wait state rom.Now OR1200 execute one > > > instruction in two period in average.So I think removing the wishbone > > > handshake will improve the performence and will execute one > instruction > > > in one period in average.Is it possible to do that? > > > Please correct me if I am wrong. > > > > > > Regards > > > _______________________________________________ > > > http://www.opencores.org/mailman/listinfo/openrisc > > > > _______________________________________________ > > http://www.opencores.org/mailman/listinfo/openrisc > > > > > > > > _______________________________________________ > > http://www.opencores.org/mailman/listinfo/openrisc > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/openrisc > > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/openrisc _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc

OR1200 wishbone problem by Unknown on Jan 10, 2004			Not available!
Hi Damjan Another question: Can I put all insn hex code into qmem and remove the insn wishbone interface? Only fetch insn from qmem on reset? Thanks and Regards ----- Original Message ----- From: "Liu Zhigang" <<A HREF="mailto:305liuzg@163.net">305liuzg@163.net</A>> To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> Sent: Saturday, January 10, 2004 11:06 AM Subject: Re: [openrisc] OR1200 wishbone problem [q] ----- Original Message ----- From: "Damjan Lampret" <<A HREF="mailto:lampret@opencores.org">lampret@opencores.org</A>> To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> Sent: Saturday, January 10, 2004 1:15 AM Subject: Re: [openrisc] OR1200 wishbone problem [q]> Hi ! > > Not with WB. But there is QMEM integrated in the OR1200 exactly for this > purpose. To have RISC w/o caches but with fixed memory (ROM or RAM) being > able to execute insns 1 per clock cycle. Look at or1200_defines.v if you > have define OR1200_QMEM_IMPLEMENTED enabled. Then just instantiate your > ROM/RAM from your library in file or1200_qmem_top.v (instance name in > current file is or1200_qmem_ram). If you don't have or1200_qmem_top.v file > then you don't have branch_qmem branch of the OR1200 sources and you should > download them !! > > regards, > Damjan > > ----- Original Message ----- > From: "Liu Zhigang" <<A HREF="mailto:305liuzg@163.net">305liuzg@163.net</A>> > To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > Sent: Friday, January 09, 2004 6:03 PM > Subject: Re: [openrisc] OR1200 wishbone problem > > [q] > Hi Damjan > Is It possible to the special memory using WB to make > instruction execution with 0 wait state? > And then it can takes only one clock periods to finish one instruction! > > Regards > > ----- Original Message ----- > From: "Damjan Lampret" <<A HREF="mailto:lampret@opencores.org">lampret@opencores.org</A>> > To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > Sent: Friday, January 09, 2004 11:40 PM > Subject: Re: [openrisc] OR1200 wishbone problem > > [q]> > Hi ! > > > > QMEM doesn't use WB. QMEM is inside OR1200. Make sure you download[/q] > or1200 [q]> > from branch branch_qmem! > > > > regards, > > Damjan > > > > ----- Original Message ----- > > From: "Liu Zhigang" <<A HREF="mailto:305liuzg@163.net">305liuzg@163.net</A>> > > To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > > Sent: Friday, January 09, 2004 4:32 PM > > Subject: Re: [openrisc] OR1200 wishbone problem > > > > [q] > > Hi > > I use WB to connect embedded QMEM as insn rom. > > But it also takes two clock periods to finish one instruction in the[/q] > RTL [q]> > simulation. [q] > > > > Regards > > > > > > ----- Original Message ----- > > From: "Damjan Lampret" <<A HREF="mailto:lampret@opencores.org">lampret@opencores.org</A>> > > To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > > Sent: Friday, January 09, 2004 10:02 PM > > Subject: Re: [openrisc] OR1200 wishbone problem > > > > [q]> > > Hi ! > > > > > > WB is used as on-chip interconnect bus. For max performance either[/q] > use [q]> > insn [q]> > > and data cache, or use embedded QMEM. If you use external RAM then > > > performance is not optiomal. > > > > > > regards, > > > Damjan > > > > > > ----- Original Message ----- > > > From: <<A HREF="mailto:lzg@gddc.com.cn">lzg@gddc.com.cn</A>> > > > To: <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > > > Sent: Friday, January 09, 2004 2:21 PM > > > Subject: [openrisc] OR1200 wishbone problem > > > > > > [q] > > > Hi > > > Now OR1200 use wishbone interface.The handshake of wishbone cost[/q] > at [q] > > > least one period,so it takes two clock periods to finish one[/q] > > instruction [q]> > > in [q] > > > average even using zero wait state rom.Now OR1200 execute one > > > instruction in two period in average.So I think removing the[/q] > wishbone [q] > > > handshake will improve the performence and will execute one[/q] > > instruction [q] > > > in one period in average.Is it possible to do that? > > > Please correct me if I am wrong. > > > > > > Regards > > > _______________________________________________ > > > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A>[/q] > > > > > > _______________________________________________ > > > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> > > > > > >[/q] > > > > _______________________________________________ > > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A>[/q] > > > > _______________________________________________ > > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> > >[/q] > > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A>[/q] > > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> > > [/q] [/q] Hi Damjan Another question: Can I put all insn hex code into qmem and remove the insn wishbone interface? Only fetch insn from qmem on reset? Thanks and Regards ----- Original Message ----- From: "Liu Zhigang" 305liuzg@163.net> To: "List about OpenRISC project" openrisc@opencores.org> Sent: Saturday, January 10, 2004 11:06 AM Subject: Re: [openrisc] OR1200 wishbone problem ----- Original Message ----- From: "Damjan Lampret" lampret@opencores.org> To: "List about OpenRISC project" openrisc@opencores.org> Sent: Saturday, January 10, 2004 1:15 AM Subject: Re: [openrisc] OR1200 wishbone problem > Hi ! > > Not with WB. But there is QMEM integrated in the OR1200 exactly for this > purpose. To have RISC w/o caches but with fixed memory (ROM or RAM) being > able to execute insns 1 per clock cycle. Look at or1200_defines.v if you > have define OR1200_QMEM_IMPLEMENTED enabled. Then just instantiate your > ROM/RAM from your library in file or1200_qmem_top.v (instance name in > current file is or1200_qmem_ram). If you don't have or1200_qmem_top.v file > then you don't have branch_qmem branch of the OR1200 sources and you should > download them !! > > regards, > Damjan > > ----- Original Message ----- > From: "Liu Zhigang" 305liuzg@163.net> > To: "List about OpenRISC project" openrisc@opencores.org> > Sent: Friday, January 09, 2004 6:03 PM > Subject: Re: [openrisc] OR1200 wishbone problem > > > Hi Damjan > Is It possible to the special memory using WB to make > instruction execution with 0 wait state? > And then it can takes only one clock periods to finish one instruction! > > Regards > > ----- Original Message ----- > From: "Damjan Lampret" lampret@opencores.org> > To: "List about OpenRISC project" openrisc@opencores.org> > Sent: Friday, January 09, 2004 11:40 PM > Subject: Re: [openrisc] OR1200 wishbone problem > > > > Hi ! > > > > QMEM doesn't use WB. QMEM is inside OR1200. Make sure you download > or1200 > > from branch branch_qmem! > > > > regards, > > Damjan > > > > ----- Original Message ----- > > From: "Liu Zhigang" 305liuzg@163.net> > > To: "List about OpenRISC project" openrisc@opencores.org> > > Sent: Friday, January 09, 2004 4:32 PM > > Subject: Re: [openrisc] OR1200 wishbone problem > > > > > > Hi > > I use WB to connect embedded QMEM as insn rom. > > But it also takes two clock periods to finish one instruction in the > RTL > > simulation. > > > > Regards > > > > > > ----- Original Message ----- > > From: "Damjan Lampret" lampret@opencores.org> > > To: "List about OpenRISC project" openrisc@opencores.org> > > Sent: Friday, January 09, 2004 10:02 PM > > Subject: Re: [openrisc] OR1200 wishbone problem > > > > > > > Hi ! > > > > > > WB is used as on-chip interconnect bus. For max performance either > use > > insn > > > and data cache, or use embedded QMEM. If you use external RAM then > > > performance is not optiomal. > > > > > > regards, > > > Damjan > > > > > > ----- Original Message ----- > > > From: lzg@gddc.com.cn> > > > To: openrisc@opencores.org> > > > Sent: Friday, January 09, 2004 2:21 PM > > > Subject: [openrisc] OR1200 wishbone problem > > > > > > > > > Hi > > > Now OR1200 use wishbone interface.The handshake of wishbone cost > at > > > least one period,so it takes two clock periods to finish one > > instruction > > > in > > > average even using zero wait state rom.Now OR1200 execute one > > > instruction in two period in average.So I think removing the > wishbone > > > handshake will improve the performence and will execute one > > instruction > > > in one period in average.Is it possible to do that? > > > Please correct me if I am wrong. > > > > > > Regards > > > _______________________________________________ > > > http://www.opencores.org/mailman/listinfo/openrisc > > > > > > _______________________________________________ > > > http://www.opencores.org/mailman/listinfo/openrisc > > > > > > > > > > _______________________________________________ > > http://www.opencores.org/mailman/listinfo/openrisc > > > > _______________________________________________ > > http://www.opencores.org/mailman/listinfo/openrisc > > > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/openrisc > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/openrisc > >

OR1200 wishbone problem by Unknown on Jan 10, 2004			Not available!
Hi ! You would have to put qmem base address at 0 and put reset vector in qmem. qmem would have to be ROM. regards, Damjan ----- Original Message ----- From: "Liu Zhigang" <<A HREF="mailto:305liuzg@163.net">305liuzg@163.net</A>> To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> Sent: Saturday, January 10, 2004 4:08 AM Subject: Re: [openrisc] OR1200 wishbone problem [q] Hi Damjan Another question: Can I put all insn hex code into qmem and remove the insn wishbone[/q] interface? [q] Only fetch insn from qmem on reset? Thanks and Regards ----- Original Message ----- From: "Liu Zhigang" <<A HREF="mailto:305liuzg@163.net">305liuzg@163.net</A>> To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> Sent: Saturday, January 10, 2004 11:06 AM Subject: Re: [openrisc] OR1200 wishbone problem [q]> > ----- Original Message ----- > From: "Damjan Lampret" <<A HREF="mailto:lampret@opencores.org">lampret@opencores.org</A>> > To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > Sent: Saturday, January 10, 2004 1:15 AM > Subject: Re: [openrisc] OR1200 wishbone problem > > [q] > Hi ! > > Not with WB. But there is QMEM integrated in the OR1200 exactly for[/q] this [q] > purpose. To have RISC w/o caches but with fixed memory (ROM or RAM)[/q] being [q] > able to execute insns 1 per clock cycle. Look at or1200_defines.v if[/q] you [q] > have define OR1200_QMEM_IMPLEMENTED enabled. Then just instantiate[/q] your [q] > ROM/RAM from your library in file or1200_qmem_top.v (instance name in > current file is or1200_qmem_ram). If you don't have or1200_qmem_top.v[/q] file [q] > then you don't have branch_qmem branch of the OR1200 sources and you[/q] should [q] > download them !! > > regards, > Damjan > > ----- Original Message ----- > From: "Liu Zhigang" <<A HREF="mailto:305liuzg@163.net">305liuzg@163.net</A>> > To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > Sent: Friday, January 09, 2004 6:03 PM > Subject: Re: [openrisc] OR1200 wishbone problem > > [q]> > Hi Damjan > > Is It possible to the special memory using WB to make > > instruction execution with 0 wait state? > > And then it can takes only one clock periods to finish one[/q] instruction! [q]> > > > Regards > > > > ----- Original Message ----- > > From: "Damjan Lampret" <<A HREF="mailto:lampret@opencores.org">lampret@opencores.org</A>> > > To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > > Sent: Friday, January 09, 2004 11:40 PM > > Subject: Re: [openrisc] OR1200 wishbone problem > > > > [q] > > Hi ! > > > > QMEM doesn't use WB. QMEM is inside OR1200. Make sure you download[/q] > or1200 [q] > > from branch branch_qmem! > > > > regards, > > Damjan > > > > ----- Original Message ----- > > From: "Liu Zhigang" <<A HREF="mailto:305liuzg@163.net">305liuzg@163.net</A>> > > To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > > Sent: Friday, January 09, 2004 4:32 PM > > Subject: Re: [openrisc] OR1200 wishbone problem > > > > [q]> > > Hi > > > I use WB to connect embedded QMEM as insn rom. > > > But it also takes two clock periods to finish one instruction[/q] in the [q] > RTL [q] > > simulation. [q]> > > > > > Regards > > > > > > > > > ----- Original Message ----- > > > From: "Damjan Lampret" <<A HREF="mailto:lampret@opencores.org">lampret@opencores.org</A>> > > > To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > > > Sent: Friday, January 09, 2004 10:02 PM > > > Subject: Re: [openrisc] OR1200 wishbone problem > > > > > > [q] > > > Hi ! > > > > > > WB is used as on-chip interconnect bus. For max performance[/q] either [q] > use [q] > > insn [q] > > > and data cache, or use embedded QMEM. If you use external RAM[/q] then [q] > > > performance is not optiomal. > > > > > > regards, > > > Damjan > > > > > > ----- Original Message ----- > > > From: <<A HREF="mailto:lzg@gddc.com.cn">lzg@gddc.com.cn</A>> > > > To: <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> > > > Sent: Friday, January 09, 2004 2:21 PM > > > Subject: [openrisc] OR1200 wishbone problem > > > > > > [q]> > > > Hi > > > > Now OR1200 use wishbone interface.The handshake of wishbone[/q] cost [q] > at [q]> > > > least one period,so it takes two clock periods to finish one[/q] > > instruction [q] > > > in [q]> > > > average even using zero wait state rom.Now OR1200 execute[/q] one [q]> > > > instruction in two period in average.So I think removing the[/q] > wishbone [q]> > > > handshake will improve the performence and will execute one[/q] > > instruction [q]> > > > in one period in average.Is it possible to do that? > > > > Please correct me if I am wrong. > > > > > > > > Regards > > > > _______________________________________________ > > > > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A>[/q] > > > > > > _______________________________________________ > > > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> > > > > > >[/q] > > > > > > _______________________________________________ > > > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A>[/q] > > > > _______________________________________________ > > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> > >[/q] > > > > _______________________________________________ > > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A>[/q] > > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> > >[/q] >[/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A>[/q] Hi ! You would have to put qmem base address at 0 and put reset vector in qmem. qmem would have to be ROM. regards, Damjan ----- Original Message ----- From: "Liu Zhigang" 305liuzg@163.net> To: "List about OpenRISC project" openrisc@opencores.org> Sent: Saturday, January 10, 2004 4:08 AM Subject: Re: [openrisc] OR1200 wishbone problem Hi Damjan Another question: Can I put all insn hex code into qmem and remove the insn wishbone interface? Only fetch insn from qmem on reset? Thanks and Regards ----- Original Message ----- From: "Liu Zhigang" 305liuzg@163.net> To: "List about OpenRISC project" openrisc@opencores.org> Sent: Saturday, January 10, 2004 11:06 AM Subject: Re: [openrisc] OR1200 wishbone problem > > ----- Original Message ----- > From: "Damjan Lampret" lampret@opencores.org> > To: "List about OpenRISC project" openrisc@opencores.org> > Sent: Saturday, January 10, 2004 1:15 AM > Subject: Re: [openrisc] OR1200 wishbone problem > > > Hi ! > > Not with WB. But there is QMEM integrated in the OR1200 exactly for this > purpose. To have RISC w/o caches but with fixed memory (ROM or RAM) being > able to execute insns 1 per clock cycle. Look at or1200_defines.v if you > have define OR1200_QMEM_IMPLEMENTED enabled. Then just instantiate your > ROM/RAM from your library in file or1200_qmem_top.v (instance name in > current file is or1200_qmem_ram). If you don't have or1200_qmem_top.v file > then you don't have branch_qmem branch of the OR1200 sources and you should > download them !! > > regards, > Damjan > > ----- Original Message ----- > From: "Liu Zhigang" 305liuzg@163.net> > To: "List about OpenRISC project" openrisc@opencores.org> > Sent: Friday, January 09, 2004 6:03 PM > Subject: Re: [openrisc] OR1200 wishbone problem > > > > Hi Damjan > > Is It possible to the special memory using WB to make > > instruction execution with 0 wait state? > > And then it can takes only one clock periods to finish one instruction! > > > > Regards > > > > ----- Original Message ----- > > From: "Damjan Lampret" lampret@opencores.org> > > To: "List about OpenRISC project" openrisc@opencores.org> > > Sent: Friday, January 09, 2004 11:40 PM > > Subject: Re: [openrisc] OR1200 wishbone problem > > > > > > Hi ! > > > > QMEM doesn't use WB. QMEM is inside OR1200. Make sure you download > or1200 > > from branch branch_qmem! > > > > regards, > > Damjan > > > > ----- Original Message ----- > > From: "Liu Zhigang" 305liuzg@163.net> > > To: "List about OpenRISC project" openrisc@opencores.org> > > Sent: Friday, January 09, 2004 4:32 PM > > Subject: Re: [openrisc] OR1200 wishbone problem > > > > > > > Hi > > > I use WB to connect embedded QMEM as insn rom. > > > But it also takes two clock periods to finish one instruction in the > RTL > > simulation. > > > > > > Regards > > > > > > > > > ----- Original Message ----- > > > From: "Damjan Lampret" lampret@opencores.org> > > > To: "List about OpenRISC project" openrisc@opencores.org> > > > Sent: Friday, January 09, 2004 10:02 PM > > > Subject: Re: [openrisc] OR1200 wishbone problem > > > > > > > > > Hi ! > > > > > > WB is used as on-chip interconnect bus. For max performance either > use > > insn > > > and data cache, or use embedded QMEM. If you use external RAM then > > > performance is not optiomal. > > > > > > regards, > > > Damjan > > > > > > ----- Original Message ----- > > > From: lzg@gddc.com.cn> > > > To: openrisc@opencores.org> > > > Sent: Friday, January 09, 2004 2:21 PM > > > Subject: [openrisc] OR1200 wishbone problem > > > > > > > > > > Hi > > > > Now OR1200 use wishbone interface.The handshake of wishbone cost > at > > > > least one period,so it takes two clock periods to finish one > > instruction > > > in > > > > average even using zero wait state rom.Now OR1200 execute one > > > > instruction in two period in average.So I think removing the > wishbone > > > > handshake will improve the performence and will execute one > > instruction > > > > in one period in average.Is it possible to do that? > > > > Please correct me if I am wrong. > > > > > > > > Regards > > > > _______________________________________________ > > > > http://www.opencores.org/mailman/listinfo/openrisc > > > > > > _______________________________________________ > > > http://www.opencores.org/mailman/listinfo/openrisc > > > > > > > > > > > > _______________________________________________ > > > http://www.opencores.org/mailman/listinfo/openrisc > > > > _______________________________________________ > > http://www.opencores.org/mailman/listinfo/openrisc > > > > > > _______________________________________________ > > http://www.opencores.org/mailman/listinfo/openrisc > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/openrisc > > > _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc

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