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spartan-3 lc board

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spartan-3 lc board by Unknown on Jan 12, 2004			Not available!
Good evening (o; Please bare in mind that I just subscribed to this mailing list and therefore I am bloody new to FPGA stuff and IP cores (o; Saw lately that Memec has a Spartan 3 LC development board which can take an interface board with SRAM/Flash, RS232 and 10/100MBit MAC...so I was thinking this might be an inexpensive way to start developing (uC)linux on the OpenRISC core... Anyone one done the OR1k on Spartan 3 devices? thanx in advance rick Good evening (o; Please bare in mind that I just subscribed to this mailing list and therefore I am bloody new to FPGA stuff and IP cores (o; Saw lately that Memec has a Spartan 3 LC development board which can take an interface board with SRAM/Flash, RS232 and 10/100MBit MAC...so I was thinking this might be an inexpensive way to start developing (uC)linux on the OpenRISC core... Anyone one done the OR1k on Spartan 3 devices? thanx in advance rick

spartan-3 lc board by Unknown on Jan 13, 2004			Not available!
[q] Good evening (o; Please bare in mind that I just subscribed to this mailing list and therefore I am bloody new to FPGA stuff and IP cores (o; Saw lately that Memec has a Spartan 3 LC development board which can take an interface board with SRAM/Flash, RS232 and 10/100MBit MAC...so I was thinking this might be an inexpensive way to start developing (uC)linux on the OpenRISC core... Anyone one done the OR1k on Spartan 3 devices? [/q] Seems this mailing list is more about gcc issues (o; Can someone give me some simple directions what ressources the or1200 core takes including 10/100 ether, sdram, flash controller and 2 channel UART? Can I just grab all the sources with minor modifications and feed them to WebPack ISE6.1 and look what devices would fit? kiitoksia rick Good evening (o; Please bare in mind that I just subscribed to this mailing list and therefore I am bloody new to FPGA stuff and IP cores (o; Saw lately that Memec has a Spartan 3 LC development board which can take an interface board with SRAM/Flash, RS232 and 10/100MBit MAC...so I was thinking this might be an inexpensive way to start developing (uC)linux on the OpenRISC core... Anyone one done the OR1k on Spartan 3 devices? Seems this mailing list is more about gcc issues (o; Can someone give me some simple directions what ressources the or1200 core takes including 10/100 ether, sdram, flash controller and 2 channel UART? Can I just grab all the sources with minor modifications and feed them to WebPack ISE6.1 and look what devices would fit? kiitoksia rick

spartan-3 lc board by Unknown on Jan 13, 2004			Not available!
I did a similar thing to what you want to do earlier in the year with a Digilent board with a 300k Spartan IIe. You should be able to find some of my posts in the archive. I used the Xilinx WebPack. I just barely had enough room to get openrisc running with uclinux and simple serial access. With 400k gates you should have room for what I did and then some. I did a similar thing to what you want to do earlier in the year with a Digilent board with a 300k Spartan IIe. You should be able to find some of my posts in the archive. I used the Xilinx WebPack. I just barely had enough room to get openrisc running with uclinux and simple serial access. With 400k gates you should have room for what I did and then some.

spartan-3 lc board by Unknown on Jan 13, 2004			Not available!
[q] I did a similar thing to what you want to do earlier in the year with[/q] a [q] Digilent board with a 300k Spartan IIe. You should be able to find[/q] some [q] of my posts in the archive. I used the Xilinx WebPack. I just barely[/q] had [q] enough room to get openrisc running with uclinux and simple serial access. With 400k gates you should have room for what I did and then some. [/q] So basically I just grab the orp_soc sources and modify "xsv_fpga_top.v" and "xsv_fpga_defines.v" and off I go? (o; Probably not... rick (bloody beginner but good at uclinux drivers/toolchains ;o) I did a similar thing to what you want to do earlier in the year with a Digilent board with a 300k Spartan IIe. You should be able to find some of my posts in the archive. I used the Xilinx WebPack. I just barely had enough room to get openrisc running with uclinux and simple serial access. With 400k gates you should have room for what I did and then some. So basically I just grab the orp_soc sources and modify "xsv_fpga_top.v" and "xsv_fpga_defines.v" and off I go? (o; Probably not... rick (bloody beginner but good at uclinux drivers/toolchains ;o)

spartan-3 lc board by Unknown on Jan 13, 2004			Not available!
Basically this is what you have to do. But I always had problems using ISE for synthesis. You might have problems. In fact in your latest email from you I see you seem to have problems similar to what happened to me whenever using ISE. So I use Synplify instead. I know it will also work just nicely with Mentor or Synopsys. I personally prefer Synplicity Synplify for synthesis. regards, Damjan ----- Original Message ----- From: "Richard Klingler" <<A HREF="mailto:richard.klingler@violasystems.com">richard.klingler@violasystems.com</A>> To: "List about OpenRISC project" <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> Sent: Tuesday, January 13, 2004 6:34 PM Subject: Re: [openrisc] spartan-3 lc board [q]> I did a similar thing to what you want to do earlier in the year with[/q] a [q]> Digilent board with a 300k Spartan IIe. You should be able to find[/q] some [q]> of my posts in the archive. I used the Xilinx WebPack. I just barely[/q] had [q]> enough room to get openrisc running with uclinux and simple serial > access. With 400k gates you should have room for what I did and then > some. >[/q] So basically I just grab the orp_soc sources and modify "xsv_fpga_top.v" and "xsv_fpga_defines.v" and off I go? (o; Probably not... rick (bloody beginner but good at uclinux drivers/toolchains ;o) _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A>[/q] Basically this is what you have to do. But I always had problems using ISE for synthesis. You might have problems. In fact in your latest email from you I see you seem to have problems similar to what happened to me whenever using ISE. So I use Synplify instead. I know it will also work just nicely with Mentor or Synopsys. I personally prefer Synplicity Synplify for synthesis. regards, Damjan ----- Original Message ----- From: "Richard Klingler" richard.klingler@violasystems.com> To: "List about OpenRISC project" openrisc@opencores.org> Sent: Tuesday, January 13, 2004 6:34 PM Subject: Re: [openrisc] spartan-3 lc board > I did a similar thing to what you want to do earlier in the year with a > Digilent board with a 300k Spartan IIe. You should be able to find some > of my posts in the archive. I used the Xilinx WebPack. I just barely had > enough room to get openrisc running with uclinux and simple serial > access. With 400k gates you should have room for what I did and then > some. > So basically I just grab the orp_soc sources and modify "xsv_fpga_top.v" and "xsv_fpga_defines.v" and off I go? (o; Probably not... rick (bloody beginner but good at uclinux drivers/toolchains ;o) _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc

spartan-3 lc board by Unknown on Jan 14, 2004			Not available!
It has been several months since I have worked with the cpu on my board. I have pushed onto some other projects.However even with 400k you will probably find yourself having to trim items to make space. When you start assembling for all the system cores, you will probably not have space for all of them. One thing that frees up quite a bit of space is traffic cop. Get rid of unused targets or initiators. Also you will probably have to trim off things from the cpu like the debugger, mmu and multiplier.Those will be in the define files. If you are just getting started and have not worked with gate arrays, you may actually want to start a bit simpler. After some really simple intro projects like flashing leds, I started out by getting the risc16f84 to work. After that I got the openrisc running off the block ram and got to where I could compile simple programs with gcc. After that I went for the full SOC. One limitation you will run into with webpack is the simulator. It intentionally slows down after you get beyond a certain size. So you will not be able to reasonably simulate your entire SOC except for some very simple test cases. It still comes in handy. What helped me the most was ORP Sim. That allowed me to see what my board should be doing when it was not. At 07:34 PM 1/13/2004 +0200, you wrote: [q] I did a similar thing to what you want to do earlier in the year with[/q] a [q] Digilent board with a 300k Spartan IIe. You should be able to find[/q] some [q] of my posts in the archive. I used the Xilinx WebPack. I just barely[/q] had [q] enough room to get openrisc running with uclinux and simple serial access. With 400k gates you should have room for what I did and then some. [/q] So basically I just grab the orp_soc sources and modify "xsv_fpga_top.v" and "xsv_fpga_defines.v" and off I go? (o; Probably not... rick (bloody beginner but good at uclinux drivers/toolchains ;o) _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> [/q] It has been several months since I have worked with the cpu on my board. I have pushed onto some other projects.However even with 400k you will probably find yourself having to trim items to make space. When you start assembling for all the system cores, you will probably not have space for all of them. One thing that frees up quite a bit of space is traffic cop. Get rid of unused targets or initiators. Also you will probably have to trim off things from the cpu like the debugger, mmu and multiplier.Those will be in the define files. If you are just getting started and have not worked with gate arrays, you may actually want to start a bit simpler. After some really simple intro projects like flashing leds, I started out by getting the risc16f84 to work. After that I got the openrisc running off the block ram and got to where I could compile simple programs with gcc. After that I went for the full SOC. One limitation you will run into with webpack is the simulator. It intentionally slows down after you get beyond a certain size. So you will not be able to reasonably simulate your entire SOC except for some very simple test cases. It still comes in handy. What helped me the most was ORP Sim. That allowed me to see what my board should be doing when it was not. At 07:34 PM 1/13/2004 +0200, you wrote: I did a similar thing to what you want to do earlier in the year with a Digilent board with a 300k Spartan IIe. You should be able to find some of my posts in the archive. I used the Xilinx WebPack. I just barely had enough room to get openrisc running with uclinux and simple serial access. With 400k gates you should have room for what I did and then some. So basically I just grab the orp_soc sources and modify "xsv_fpga_top.v" and "xsv_fpga_defines.v" and off I go? (o; Probably not... rick (bloody beginner but good at uclinux drivers/toolchains ;o) _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc

spartan-3 lc board by Unknown on Jan 14, 2004			Not available!
[q] Basically this is what you have to do. But I always had problems using ISE for synthesis. You might have problems. In fact in your latest email from you I see you seem to have problems similar to what happened to me whenever using ISE. So I use Synplify instead. I know it will also work just nicely with Mentor or Synopsys. I personally prefer Synplicity Synplify for synthesis. regards, Damjan[/q] Just tried with a simple design...well...usb1_core (o; Compiled out of the box with Altera Quartus but no chance with ISE6.1...some strange $PATH issues maybe... btw: downloading usb1_core and usb_phy resulted in an empty tar.gz file...web cvs checkout worked... best regards rick Basically this is what you have to do. But I always had problems using ISE for synthesis. You might have problems. In fact in your latest email from you I see you seem to have problems similar to what happened to me whenever using ISE. So I use Synplify instead. I know it will also work just nicely with Mentor or Synopsys. I personally prefer Synplicity Synplify for synthesis. regards, Damjan Just tried with a simple design...well...usb1_core (o; Compiled out of the box with Altera Quartus but no chance with ISE6.1...some strange $PATH issues maybe... btw: downloading usb1_core and usb_phy resulted in an empty tar.gz file...web cvs checkout worked... best regards rick

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