Someone can put a light on:

ssvga_fifo.v: Error: Node instance ramb4_s8_0 instantiates undefined
entity RAMB4_S8_S16


an equivalent to Altera's version of RAMB?


rick

Had to disable vga and debug...

Now next error pops up which I have no clue so far:

or1200_cup.v:

Port genpc_stop_prefetch does not exist in macrofunction or1200_genpc


thanx for some hints...
rick

If it takes more than an hour you must be doing something wrong, ie like instantiating flops instead of block RAMs for all the memories. Or have too aggresive constraints. regards, Damjan ----- Original Message ----- From: "Richard Klingler" richard.klingler@violasystems.com> To: "List about OpenRISC project" openrisc@opencores.org> Sent: Wednesday, January 14, 2004 5:35 PM Subject: Re: [openrisc] orp_soc compile on quartus... Oki...just not defined in or1200_genpc.v... Just commented out in or1200_cpu.v by now and waiting for synthesis to finish or fail again... btw: how long does it takes for orp_soc on athlon xp2600+? (o; rick _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc

Oki...just not defined in or1200_genpc.v...

Just commented out in or1200_cpu.v by now and waiting for synthesis to
finish or
fail again...

btw: how long does it takes for orp_soc on athlon xp2600+? (o;


rick

like

have


Hmm...quartus doesn't output very much information during synthesis...


Someone got also quartus for verifying the changes I've made?


rick

Uploaded my quartus stuff to: http://www.uclinux.net/download/orp_soc.tar.gz If someone else wants to try... thanx in advance rick