ORP.txt says there is 1G RAM at address 0x0. OR1000 wants to find its
reset vector at addr 0x100. So obviously, steps must be taken to have
program code available in the RAM area after reset.

The ORP HDL code mirrors the ROM temporarily to address 0x0. So that is
a possible solution. Still I don't understand why ORP places RAM at the
processors reset address.

But that scheme doesn't work on the or1ksim, which doesn't do the
mirroring. Does that mean I have to build a seperate executable for use
with or1ksim?

Heiko

Heiko,

no, you should use exactly the same executable on or1ksim and your HW.
What is usually done is than when system starts, MC (momory controller) is not
inicialized and flash is seen all over the address map. Therefore or1k has no
problems booting from 0x100. Next, or1k jumps to the address where flash will
reside after the inicialization of MC. MC inicialization is done and RAM gets
visible at 0. Next, .data and .bss and possibly some other sections as well
gets copied and initialized. Then program jumps to "main" routine of C
program or some other startup routine, which calls "main".

You have examples how this functions in basically all or1k programs, e.g.
orpmon.

hope it helps,
Marko

On Thursday 22 January 2004 16:12, Heiko Panther wrote:

Does or1ksim simulate this behaviour? What do I have to do so this
behaviour is simulated? Are the sim.cfg "ce" properties of the memory
areas important for this?

Heiko

Yes!

On Friday 23 January 2004 13:30, Heiko Panther wrote:
Does or1ksim simulate this behaviour? What do I have to do so this behaviour is simulated? Are the sim.cfg "ce" properties of the memory areas important for this? Heiko _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc

> Yes!

Could you explain how the "ce" properties work and what general steps I
have to take (with memory regions, memory controller settings etc.) to
achieve the mirror effect? I'm going to put that info into the READMEs
for later reference then.

Heiko

CEs are numbered as you specify them in sim.cfg.

See memory controller doc for more details.

Marko

On Friday 23 January 2004 18:40, Heiko Panther wrote:
Could you explain how the "ce" properties work and what general steps I have to take (with memory regions, memory controller settings etc.) to achieve the mirror effect? I'm going to put that info into the READMEs for later reference then. Heiko _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc

huh, sorry, I though it has this option.

But it is not so hard to add it:
In except.c, except_handle: just logical-or the ea (effective address) with
0xf0000000. Maybe we should put it under sim.cfg?

Marko

On Wednesday 04 February 2004 14:23, you wrote:

Marko Mlinar wrote:


There is a way to do this from or1ksim. There's an option to set the
initial contents of the SR register. If you set the EPH (Exception
Prefix High) bit, the simulator will boot at 0xf0000100. (I'm sorry I
don't have access to my files now so I can't relate the exact syntax.)

-Scott