I noticed that the copy of eCos in the repository is not up to date. In particular, it is missing the patches that I submitted to the ecos-patches mailing list in May, 2003. The differences (attached) are almost entirely cleanup items suggested to me by the eCos maintainers and though the patches are not trivial, virtually no code is actually changed as a result. However, I don't want to change eCos now and create an unstable situation for those that are trying to get it to build/run reliably. When that's over, I would like to incorporate the latest patches into the OC repository - unless anyone has objections... -Scott -------------- next part -------------- diff -x CVS -c -r ./packages/hal/openrisc/arch/current/cdl/hal_openrisc.cdl /home/sfurman/ecos/packages/hal/openrisc/arch/current/cdl/hal_openrisc.cdl *** ./packages/hal/openrisc/arch/current/cdl/hal_openrisc.cdl 2003-05-07 20:50:02.000000000 -0700 --- /home/sfurman/ecos/packages/hal/openrisc/arch/current/cdl/hal_openrisc.cdl 2003-06-11 14:15:37.000000000 -0700 *************** *** 109,111 **** --- 109,113 ---- memory access speed settings." } } + + # EOF hal_openrisc.cdl diff -x CVS -c -r ./packages/hal/openrisc/arch/current/ChangeLog /home/sfurman/ecos/packages/hal/openrisc/arch/current/ChangeLog *** ./packages/hal/openrisc/arch/current/ChangeLog 2003-05-07 20:50:02.000000000 -0700 --- /home/sfurman/ecos/packages/hal/openrisc/arch/current/ChangeLog 2003-06-17 20:24:00.000000000 -0700 *************** *** 1,3 **** --- 1,39 ---- + 2003-05-15 Scott Furman sfurman@rosum.com> + + * src/vectors.S: Add a distinctive (non-0xFF) word at the + beginning of the ROM, so that the RedBoot 'fis free' command does + not mistakenly think that the first sector of the Flash ROM is + empty. Remove tab characters that somehow snuck into the file. + + 2003-05-05 Scott Furman sfurman@rosum.com> + + * src/vectors.S: Made it possible for a platform to override + architecture defaults for the selection of ISR based on interrupt + controller state, i.e.so that a platform-specific interrupt + controller could be used or interrupt priorities set differently. + Made it possible for a platform to override the default + architecture exception/reset vector location. + + * src/openrisc.ld: Removed libsupc++ requirement, as it does not + yet compile for OpenRISC. Added underscore prefixes to symbol + names, so they can be accessed from C. Made change to _edata + symbol to accommodate reshuffling of section order in platform + .ldi files. + + 2003-04-25 Jonathan Larmour jifl@eCosCentric.com> + + * src/openrisc.ld: Add some missing sections mostly just by comparison + with another HAL.. + + * include/hal_cache.h: Include hal_arch.h for MTSPR/MFSPR. + + 2003-04-17 Scott Furman sfurman@rosum.com> + + * src/vectors.S: Init tick timer on boot + * include/hal_arch.h: Ensure stack is aligned in + HAL_THREAD_INIT_CONTEXT() + * openrisc.ld: Add .text.ram section for time-critical code + 2003-03-06 Scott Furman sfurman@rosum.com> Initial port of eCos to OpenRISC architecture *************** *** 7,13 **** // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. - // Copyright (C) 2002 Gary Thomas // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free --- 43,48 ---- Only in ./packages/hal/openrisc/arch/current/doc: build_or32_elf_tools.sh diff -x CVS -c -r ./packages/hal/openrisc/arch/current/include/arch.inc /home/sfurman/ecos/packages/hal/openrisc/arch/current/include/arch.inc *** ./packages/hal/openrisc/arch/current/include/arch.inc 2003-05-07 20:50:02.000000000 -0700 --- /home/sfurman/ecos/packages/hal/openrisc/arch/current/include/arch.inc 2003-06-11 14:15:37.000000000 -0700 *************** *** 58,66 **** #ifndef CYGONCE_HAL_ARCH_INC #define CYGONCE_HAL_ARCH_INC - #include - #include - # Declare given label name as the start of a function accessible from C code #define FUNC_START(name) \ .type _##name,@function; \ --- 58,63 ---- *************** *** 103,106 **** --- 100,108 ---- #define SIZEOF_OR1KREGS (OR1KREG_EEAR + OR1K_REGSIZE) + #include + #include + #endif // #ifndef CYGONCE_HAL_ARCH_INC + + // EOF arch.inc diff -x CVS -c -r ./packages/hal/openrisc/arch/current/include/hal_arch.h /home/sfurman/ecos/packages/hal/openrisc/arch/current/include/hal_arch.h *** ./packages/hal/openrisc/arch/current/include/hal_arch.h 2003-05-07 20:50:02.000000000 -0700 --- /home/sfurman/ecos/packages/hal/openrisc/arch/current/include/hal_arch.h 2003-06-11 14:15:37.000000000 -0700 *************** *** 142,151 **** // _id_ bit pattern used in initializing registers, for debugging. #define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \ { \ - register CYG_WORD _sp_ = ((CYG_WORD)_sparg_) & 0xfffffff8; \ - register HAL_SavedRegisters *_regs_; \ int _i_; \ ! _regs_ = (HAL_SavedRegisters *)(((_sp_) - sizeof(HAL_SavedRegisters))); \ for( _i_ = 1; _i_ r[_i_] = (_id_)|_i_; \ (_regs_)->r[1] = (CYG_HAL_OPENRISC_REG)(_sp_); /* SP = top of stack */ \ (_regs_)->r[2] = (CYG_HAL_OPENRISC_REG)(_sp_); /* FP = top of stack */ \ --- 142,152 ---- // _id_ bit pattern used in initializing registers, for debugging. #define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \ { \ int _i_; \ ! register CYG_WORD _sp_ = ((CYG_WORD)_sparg_); \ ! register HAL_SavedRegisters *_regs_; \ ! _regs_ = (HAL_SavedRegisters *)(((_sp_) - sizeof(HAL_SavedRegisters)) & ~(CYGARC_ALIGNMENT));\ ! _sp_ &= ~(CYGARC_ALIGNMENT); \ for( _i_ = 1; _i_ r[_i_] = (_id_)|_i_; \ (_regs_)->r[1] = (CYG_HAL_OPENRISC_REG)(_sp_); /* SP = top of stack */ \ (_regs_)->r[2] = (CYG_HAL_OPENRISC_REG)(_sp_); /* FP = top of stack */ \ diff -x CVS -c -r ./packages/hal/openrisc/arch/current/include/hal_cache.h /home/sfurman/ecos/packages/hal/openrisc/arch/current/include/hal_cache.h *** ./packages/hal/openrisc/arch/current/include/hal_cache.h 2003-05-07 20:50:02.000000000 -0700 --- /home/sfurman/ecos/packages/hal/openrisc/arch/current/include/hal_cache.h 2003-06-11 14:15:37.000000000 -0700 *************** *** 82,87 **** --- 82,89 ---- #ifndef __ASSEMBLER__ + #include + //----------------------------------------------------------------------------- // Global control of data cache diff -x CVS -c -r ./packages/hal/openrisc/arch/current/include/hal_intr.h /home/sfurman/ecos/packages/hal/openrisc/arch/current/include/hal_intr.h *** ./packages/hal/openrisc/arch/current/include/hal_intr.h 2003-05-07 20:50:03.000000000 -0700 --- /home/sfurman/ecos/packages/hal/openrisc/arch/current/include/hal_intr.h 2003-06-13 18:00:53.000000000 -0700 *************** *** 134,139 **** --- 134,140 ---- ( CYGNUM_HAL_EXCEPTION_MAX - CYGNUM_HAL_EXCEPTION_MIN + 1 ) + // Allow platform to override interrupt numbers #ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED #define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED *************** *** 414,421 **** CYG_MACRO_START \ { \ int ttmr_new = _period_ | 0x60000000; \ ! MTSPR(SPR_TTMR, ttmr_new); \ MTSPR(SPR_TTCR, 0); \ cyg_hal_clock_period = _period_; \ } \ CYG_MACRO_END --- 415,423 ---- CYG_MACRO_START \ { \ int ttmr_new = _period_ | 0x60000000; \ ! MTSPR(SPR_TTMR, 0); \ MTSPR(SPR_TTCR, 0); \ + MTSPR(SPR_TTMR, ttmr_new); \ cyg_hal_clock_period = _period_; \ } \ CYG_MACRO_END diff -x CVS -c -r ./packages/hal/openrisc/arch/current/include/openrisc_opcode.h /home/sfurman/ecos/packages/hal/openrisc/arch/current/include/openrisc_opcode.h *** ./packages/hal/openrisc/arch/current/include/openrisc_opcode.h 2003-05-07 20:50:03.000000000 -0700 --- /home/sfurman/ecos/packages/hal/openrisc/arch/current/include/openrisc_opcode.h 2003-06-11 14:15:38.000000000 -0700 *************** *** 90,92 **** --- 90,94 ---- #define OP_JALR 0x12 #endif /* _OPENRISC_OPCODE_H */ + + // EOF openrisc_opcode.h diff -x CVS -c -r ./packages/hal/openrisc/arch/current/include/openrisc_stub.h /home/sfurman/ecos/packages/hal/openrisc/arch/current/include/openrisc_stub.h *** ./packages/hal/openrisc/arch/current/include/openrisc_stub.h 2003-05-07 20:50:03.000000000 -0700 --- /home/sfurman/ecos/packages/hal/openrisc/arch/current/include/openrisc_stub.h 2003-06-11 14:15:38.000000000 -0700 *************** *** 164,166 **** --- 164,168 ---- externC void __clear_breakpoints (void); #endif // ifndef CYGONCE_HAL_OPENRISC_STUB_H + + // EOF openrisc_stub.h diff -x CVS -c -r ./packages/hal/openrisc/arch/current/include/spr_defs.h /home/sfurman/ecos/packages/hal/openrisc/arch/current/include/spr_defs.h *** ./packages/hal/openrisc/arch/current/include/spr_defs.h 2003-05-07 20:50:03.000000000 -0700 --- /home/sfurman/ecos/packages/hal/openrisc/arch/current/include/spr_defs.h 2003-06-11 14:15:38.000000000 -0700 *************** *** 462,464 **** --- 462,466 ---- #define SPR_TTMR_M 0xc0000000 /* Tick mode */ #endif + + // EOF spr_defs.h Only in /home/sfurman/ecos/packages/hal/openrisc/arch/current: misc diff -x CVS -c -r ./packages/hal/openrisc/arch/current/src/openrisc.ld /home/sfurman/ecos/packages/hal/openrisc/arch/current/src/openrisc.ld *** ./packages/hal/openrisc/arch/current/src/openrisc.ld 2003-05-07 20:50:04.000000000 -0700 --- /home/sfurman/ecos/packages/hal/openrisc/arch/current/src/openrisc.ld 2003-07-02 14:02:11.000000000 -0700 *************** *** 53,59 **** --- 53,66 ---- #ifdef EXTRAS INPUT(extras.o) #endif + + /* FIXME: libsupc++ is not needed by eCos, but it might be needed by apps linked w/ eCos. + However, it does not yet compile for OpenRISC. */ + #if (__GNUC__ >= 3) + GROUP(libtarget.a libgcc.a /* libsupc++.a */ ) + #else GROUP(libtarget.a libgcc.a) + #endif #define ALIGN_LMA 8 #define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1)) *************** *** 63,93 **** #define SECTIONS_BEGIN #define SECTION_vectors(_region_, _vma_, _lma_) \ .vectors _vma_ : _lma_ \ { FORCE_OUTPUT; KEEP(*(.vectors)) } \ > _region_ ! #define SECTION_text(_region_, _vma_, _lma_) \ ! .text _vma_ : _lma_ \ ! { __stext = .; \ ! *(.text*) *(.gnu.warning) *(.gnu.linkonce*) *(.init) } \ ! > _region_ \ ! __etext = .; PROVIDE (etext = .); #define SECTION_fini(_region_, _vma_, _lma_) \ ! .fini _vma_ : _lma_ \ ! { FORCE_OUTPUT; *(.fini) } \ ! > _region_ #define SECTION_rodata1(_region_, _vma_, _lma_) \ ! .rodata1 _vma_ : _lma_ \ ! { FORCE_OUTPUT; *(.rodata1*) } \ > _region_ ! #define SECTION_rodata(_region_, _vma_, _lma_) \ ! .rodata _vma_ : _lma_ \ ! { FORCE_OUTPUT; *(.rodata*) } \ > _region_ #define SECTION_fixup(_region_, _vma_, _lma_) \ --- 70,200 ---- #define SECTIONS_BEGIN + #define SECTION_ROMISC(_region_, _vma_, _lma_) \ + .interp _vma_ : _lma_ { *(.interp) } > _region_ \ + .hash : FOLLOWING(.interp) { *(.hash) } > _region_ \ + .dynsym : FOLLOWING(.hash) { *(.dynsym) } > _region_ \ + .dynstr : FOLLOWING(.dynsym) { *(.dynstr) } > _region_ \ + .gnu.version : FOLLOWING(.dynstr) { *(.gnu.version) } > _region_ \ + .gnu.version_d : FOLLOWING(.gnu.version) { *(.gnu.version_d) } > _region_ \ + .gnu.version_r : FOLLOWING(.gnu.version_d) { *(.gnu.version_r) } > _region_ \ + .plt : FOLLOWING(.gnu.version_r) { *(.plt) } > _region_ + + #define SECTION_eh_frame(_region_, _vma_, _lma_) \ + .eh_frame _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; __EH_FRAME_BEGIN__ = .; \ + KEEP(*(.eh_frame)) \ + __FRAME_END__ = .; \ + . = . + 8; \ + } > _region_ = 0 + + #define SECTION_RELOCS(_region_, _vma_, _lma_) \ + .rel.text : \ + { \ + *(.rel.text) \ + *(.rel.text.*) \ + *(.rel.gnu.linkonce.t*) \ + } > _region_ \ + .rela.text : \ + { \ + *(.rela.text) \ + *(.rela.text.*) \ + *(.rela.gnu.linkonce.t*) \ + } > _region_ \ + .rel.data : \ + { \ + *(.rel.data) \ + *(.rel.data.*) \ + *(.rel.gnu.linkonce.d*) \ + } > _region_ \ + .rela.data : \ + { \ + *(.rela.data) \ + *(.rela.data.*) \ + *(.rela.gnu.linkonce.d*) \ + } > _region_ \ + .rel.rodata : \ + { \ + *(.rel.rodata) \ + *(.rel.rodata.*) \ + *(.rel.gnu.linkonce.r*) \ + } > _region_ \ + .rela.rodata : \ + { \ + *(.rela.rodata) \ + *(.rela.rodata.*) \ + *(.rela.gnu.linkonce.r*) \ + } > _region_ \ + .rel.got : { *(.rel.got) } > _region_ \ + .rela.got : { *(.rela.got) } > _region_ \ + .rel.ctors : { *(.rel.ctors) } > _region_ \ + .rela.ctors : { *(.rela.ctors) } > _region_ \ + .rel.dtors : { *(.rel.dtors) } > _region_ \ + .rela.dtors : { *(.rela.dtors) } > _region_ \ + .rel.init : { *(.rel.init) } > _region_ \ + .rela.init : { *(.rela.init) } > _region_ \ + .rel.fini : { *(.rel.fini) } > _region_ \ + .rela.fini : { *(.rela.fini) } > _region_ \ + .rel.bss : { *(.rel.bss) } > _region_ \ + .rela.bss : { *(.rela.bss) } > _region_ \ + .rel.plt : { *(.rel.plt) } > _region_ \ + .rela.plt : { *(.rela.plt) } > _region_ \ + .rel.dyn : { *(.rel.dyn) } > _region_ + #define SECTION_vectors(_region_, _vma_, _lma_) \ .vectors _vma_ : _lma_ \ { FORCE_OUTPUT; KEEP(*(.vectors)) } \ > _region_ ! #define SECTION_init(_region_, _vma_, _lma_) \ ! .init _vma_ : _lma_ \ ! { \ ! FORCE_OUTPUT; KEEP (*(.init)) \ ! } > _region_ =0 #define SECTION_fini(_region_, _vma_, _lma_) \ ! .fini _vma_ : _lma_ \ ! { \ ! FORCE_OUTPUT; KEEP (*(.fini)) \ ! } > _region_ =0 ! ! // Code that might be executed out of either RAM or ROM ! #define SECTION_text(_region_, _vma_, _lma_) \ ! .text _vma_ : _lma_ \ ! { __stext = .; \ ! *(.text*) *(.gnu.warning) *(.gnu.linkonce.t.*) } \ ! > _region_ \ ! __etext = .; PROVIDE (etext = .); ! ! // The .text.ram section is for performance-sensitive code that is ! // always executed from RAM. (If the code is loaded into ROM, it will ! // be copied into RAM prior to execution.) ! // ! // Note: The SECTION_text_ram() macro must be listed in the linker ! // include script (*.ldi file) prior to SECTION_text(). ! // ! // All eCos code is put in the .text section unless explicitly placed ! // into a section named section .text.ram*. ! ! #define SECTION_text_ram(_region_, _vma_, _lma_) \ ! .text.ram _vma_ : _lma_ \ ! { __stext_ram = .; \ ! __ram_text_start = ABSOLUTE(.); \ ! *(.text.ram*) \ ! } > _region_ \ ! __load_addr_text_ram = LOADADDR(.text.ram); \ ! __ram_text_end = .; PROVIDE(__ram_text_end = .); \ ! __etext_ram = .; PROVIDE (etext_ram = .); #define SECTION_rodata1(_region_, _vma_, _lma_) \ ! .rodata1 _vma_ : _lma_ \ ! { FORCE_OUTPUT; *(.rodata1) *(.rodata1*) } \ > _region_ ! #define SECTION_rodata(_region_, _vma_, _lma_) \ ! .rodata _vma_ : _lma_ \ ! { FORCE_OUTPUT; *(.rodata) *(.rodata*) *(.gnu.linkonce.r*) } \ > _region_ #define SECTION_fixup(_region_, _vma_, _lma_) \ *************** *** 101,133 **** __EXCEPT_END__ = ABSOLUTE(.);} \ > _region_ ! #define SECTION_data(_region_, _vma_, _lma_) \ ! .data _vma_ : _lma_ \ ! { __ram_data_start = ABSOLUTE(.); *(.data*) \ ! __GOT1_START__ = ABSOLUTE(.); *(.got1) __GOT1_END__ = ABSOLUTE(.); \ ! /* Put .ctors and .dtors next to the .got2 section, so that */ \ ! /* the pointers get relocated with -mrelocatable. */ \ ! . = ALIGN(8); ___CTOR_LIST__ = ABSOLUTE(.); \ ! KEEP(*(SORT(.ctors*))) ___CTOR_END__ = ABSOLUTE(.); \ ! ___DTOR_LIST__ = ABSOLUTE(.); \ ! KEEP(*(SORT(.dtors*))) ___DTOR_END__ = ABSOLUTE(.); \ ! . = ALIGN(8); \ ! KEEP(*( SORT (.ecos.table.*))) ; \ ! . = ALIGN(4); \ ! *( .2ram.*) ; \ ! __GOT2_START__ = ABSOLUTE(.); *(.got2) __GOT2_END__ = ABSOLUTE(.); \ ! __GOT_START = ABSOLUTE(.); _GLOBAL_OFFSET_TABLE_ = ABSOLUTE(. + 32768); \ ! _SDA_BASE_ = ABSOLUTE(.); *(.got.plt) *(.got) \ ! __GOT_END__ = ABSOLUTE(.); *(.dynamic) \ ! /* We want the small data sections together, so single-instruction */ \ ! /* offsets can access them all, and initialized data all before */ \ ! /* uninitialized, so we can shorten the on-disk segment size. */ \ ! __SDATA_START__ = ABSOLUTE(.); *(.sdata) *(.sdata.*) \ ! __SDATA2_START__ = ABSOLUTE(.); *(.sdata2*) } \ ! > _region_ \ ! __rom_data_start = LOADADDR(.data); \ ! __ram_data_end = .; PROVIDE(__ram_data_end = .); \ ! _edata = .; PROVIDE (edata = .); #define SECTION_sbss(_region_, _vma_, _lma_) \ .sbss _vma_ : _lma_ \ --- 208,293 ---- __EXCEPT_END__ = ABSOLUTE(.);} \ > _region_ ! #define SECTION_ctors(_region_, _vma_, _lma_) \ ! .ctors _vma_ : _lma_ \ ! { \ ! FORCE_OUTPUT; \ ! KEEP (*crtbegin.o(.ctors)) \ ! KEEP (*_ctors.o(.ctors)) \ ! ___CTOR_LIST__ = .; \ ! PROVIDE (___CTOR_LIST__ = .); \ ! KEEP (*(.ctors)); \ ! KEEP (*(SORT(.ctors.*))) \ ! ___CTOR_END__ = .; \ ! PROVIDE (___CTOR_END__ = .); \ ! } > _region_ ! ! #define SECTION_dtors(_region_, _vma_, _lma_) \ ! .dtors _vma_ : _lma_ \ ! { \ ! FORCE_OUTPUT; \ ! KEEP (*crtbegin.o(.dtors)) \ ! ___DTOR_LIST__ = .; \ ! PROVIDE (___DTOR_LIST__ = .); \ ! KEEP (*(SORT(.dtors.*))) \ ! ___DTOR_END__ = .; \ ! KEEP (*(.dtors)); \ ! PROVIDE (___DTOR_END__ = .); \ ! } > _region_ ! ! #define SECTION_got(_region_, _vma_, _lma_) \ ! .got _vma_ : _lma_ \ ! { \ ! FORCE_OUTPUT; *(.got.plt) *(.got*) \ ! } > _region_ ! ! #define SECTION_dynamic(_region_, _vma_, _lma_) \ ! .dynamic _vma_ : _lma_ \ ! { \ ! FORCE_OUTPUT; *(.dynamic) \ ! } > _region_ ! ! #define SECTION_devtab(_region_, _vma_, _lma_) \ ! .devtab _vma_ : _lma_ \ ! { \ ! FORCE_OUTPUT; \ ! KEEP(*( SORT (.ecos.table.*))) ; \ ! } > _region_ ! ! #define SECTION_data(_region_, _vma_, _lma_) \ ! .data _vma_ : _lma_ \ ! { __ram_data_start = ABSOLUTE(.); \ ! *(.data*) *(.data.*) *(.gnu.linkonce.d*) \ ! *( .2ram.*) \ ! . = ALIGN (8); \ ! SORT(CONSTRUCTORS) \ ! } > _region_ \ ! __rom_data_start = LOADADDR(.data); ! ! /* We want the small data sections together, so single-instruction offsets ! can access them all, and initialized data all before uninitialized, so ! we can shorten the on-disk segment size. */ ! ! #define SECTION_sdata(_region_, _vma_, _lma_) \ ! .sdata _vma_ : _lma_ \ ! { \ ! __SDATA_START__ = ABSOLUTE(.); \ ! FORCE_OUTPUT; *(.sdata) *(.sdata.*) *(.gnu.linkonce.s*) \ ! } > _region_ \ ! __ram_data_end = .; __edata = . ; \ ! PROVIDE (edata = .); ! ! #define SECTION_lit8(_region_, _vma_, _lma_) \ ! .lit8 _vma_ : _lma_ \ ! { \ ! FORCE_OUTPUT; *(.lit8) \ ! } > _region_ ! ! #define SECTION_lit4(_region_, _vma_, _lma_) \ ! .lit4 : FOLLOWING(.lit8) \ ! { \ ! FORCE_OUTPUT; *(.lit4) \ ! } > _region_ \ #define SECTION_sbss(_region_, _vma_, _lma_) \ .sbss _vma_ : _lma_ \ *************** *** 140,151 **** #define SECTION_bss(_region_, _vma_, _lma_) \ .bss _vma_ : _lma_ \ ! { __bss_start = ABSOLUTE (.); \ ! FORCE_OUTPUT; *(.dynbss*) *(.bss*) *(COMMON) \ ! __bss_end = ABSOLUTE (.); } \ > _region_ ! #define SECTIONS_END . = ALIGN(4); _end = .; PROVIDE (end = .); #include #include CYGHWR_MEMORY_LAYOUT_LDI --- 300,311 ---- #define SECTION_bss(_region_, _vma_, _lma_) \ .bss _vma_ : _lma_ \ ! { __bss_start = ABSOLUTE (.); \ ! FORCE_OUTPUT; *(.dynbss*) *(.bss) *(.bss.*) *(COMMON) \ ! __bss_end = ABSOLUTE (.); } \ > _region_ ! #define SECTIONS_END . = ALIGN(4); __end = .; PROVIDE (end = .); #include #include CYGHWR_MEMORY_LAYOUT_LDI *************** *** 154,156 **** --- 314,318 ---- #include CYGBLD_HAL_TARGET_H _hal_vsr_table = CYGHWR_HAL_VSR_TABLE; _hal_virtual_vector_table = CYGHWR_HAL_VIRTUAL_VECTOR_TABLE; + + // EOF openrisc.ld diff -x CVS -c -r ./packages/hal/openrisc/arch/current/src/openrisc_stub.c /home/sfurman/ecos/packages/hal/openrisc/arch/current/src/openrisc_stub.c *** ./packages/hal/openrisc/arch/current/src/openrisc_stub.c 2003-05-07 20:50:04.000000000 -0700 --- /home/sfurman/ecos/packages/hal/openrisc/arch/current/src/openrisc_stub.c 2003-06-11 14:15:38.000000000 -0700 *************** *** 62,68 **** #include #include #include ! #include #include // assertion macros #ifdef CYGNUM_HAL_NO_VECTOR_TRACE --- 62,68 ---- #include #include #include ! #include #include // assertion macros #ifdef CYGNUM_HAL_NO_VECTOR_TRACE *************** *** 296,298 **** --- 296,299 ---- #endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + // EOF openrisc_stub.c diff -x CVS -c -r ./packages/hal/openrisc/arch/current/src/vectors.S /home/sfurman/ecos/packages/hal/openrisc/arch/current/src/vectors.S *** ./packages/hal/openrisc/arch/current/src/vectors.S 2003-05-07 20:50:05.000000000 -0700 --- /home/sfurman/ecos/packages/hal/openrisc/arch/current/src/vectors.S 2003-06-17 20:22:22.000000000 -0700 *************** *** 60,66 **** #include // CYGPKG_KERNEL_INSTRUMENT #endif - #include #include #include --- 60,65 ---- *************** *** 85,94 **** #include #include #=========================================================================== # Start by defining the exceptions vectors that must be placed in low ! # memory, starting at location 0x100. .section ".vectors","ax" --- 84,153 ---- #include #include + # + # During ROM startup, exception code is copied from ROM to this RAM address + # + #ifndef RAM_EXCEPTION_VECTOR_BASE_ADDRESS + #define RAM_EXCEPTION_VECTOR_BASE_ADDRESS 0x00000000 + #endif + + # + # This is a platform-specific macro that dispatches to an ISR based + # on the state of the interrupt controller. The default version + # below uses the PIC defined by the OpenRISC architecture. + # + # A compatible (platform-specific) override for this macro must + # preserve all callee-saved regs as well as temp reg r31. On exit, + # r3 contains the number which will be used to index the table of ISRs. + # + + #ifndef HAL_MAP_INTERRUPT_TO_ISR_DEFINED + .macro hal_map_interrupt_to_isr + + # Read the PIC interrupt controller's status register + l.mfspr r9,r0,SPR_PICSR + + # In the event of multiple pending interrupts, determine which + # one will be serviced first. By software convention, the lowest + # numbered external interrupt gets priority. + # + # The (internal) tick timer interrupt is serviced only if no + # external interrupts are pending. + + # Any pending external interrupts ? + l.sfnei r9,0 + l.bf check_for_external_interrupts + + # Theoretically, the only way we could get here is if the tick timer + # interrupt fired, but we check to be sure that's what happened. + l.sfeqi r4,CYGNUM_HAL_VECTOR_TICK_TIMER + l.bf 3f + l.ori r3,r0,CYGNUM_HAL_INTERRUPT_RTC # delay slot + + #ifndef CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS + l.jal _hal_spurious_IRQ + l.nop + #endif // CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS + l.j ignore_spurious_interrupt + + # Identify the lowest numbered interrupt bit in the PIC's PSR, + # numbering the MSB as 31 and the LSB as 0 + check_for_external_interrupts: + l.ori r3,r0,0 + 2: l.andi r11,r9,1 # Test low bit + l.sfnei r11,0 + l.bf 3f + l.srli r9,r9,1 # Shift right 1 bit + l.j 2b + l.addi r3,r3,1 # Delay slot + 3: + .endm + #endif # ifndef HAL_MAP_INTERRUPT_TO_ISR_DEFINED + #=========================================================================== # Start by defining the exceptions vectors that must be placed in low ! # memory, starting at location 0x100 by default. .section ".vectors","ax" *************** *** 158,164 **** l.sw 28 * OR1K_GPRSIZE(sp), r28 l.sw 30 * OR1K_GPRSIZE(sp), r30 ! # save MAC LO and HI regs l.mfspr r5,r0,SPR_MACLO l.sw OR1KREG_MACLO(sp),r5 l.mfspr r5,r0,SPR_MACHI --- 217,223 ---- l.sw 28 * OR1K_GPRSIZE(sp), r28 l.sw 30 * OR1K_GPRSIZE(sp), r30 ! # save MAC LO and HI regs l.mfspr r5,r0,SPR_MACLO l.sw OR1KREG_MACLO(sp),r5 l.mfspr r5,r0,SPR_MACHI *************** *** 183,189 **** l.sw OR1KREG_EEAR(sp),r5 # Second arg to VSR is exception number ! # First vector is located at 0x100, second at 0x200, etc. # Shift right to get vector number for address lookup. l.ori r4,r0,(\org>>8) l.sw OR1KREG_VECTOR(sp),r4 --- 242,248 ---- l.sw OR1KREG_EEAR(sp),r5 # Second arg to VSR is exception number ! # First vector is located at offset 0x100, second at 0x200, etc. # Shift right to get vector number for address lookup. l.ori r4,r0,(\org>>8) l.sw OR1KREG_VECTOR(sp),r4 *************** *** 199,208 **** l.or r3,r0,sp # Delay slot .endm #--------------------------------------------------------------------------- ! # Define the exception vectors. rom_vectors: # These are the architecture-defined vectors that # are always present. --- 258,275 ---- l.or r3,r0,sp # Delay slot .endm + + #ifndef CYG_HAL_STARTUP_RAM #--------------------------------------------------------------------------- ! # Add distinctive (non-0xFF) word at the beginning of the ROM, so that ! # 'fis free' does not mistakenly think the Flash sector is empty. ! .word 0xbeeff00d ! .p2align 8 ! #endif + #--------------------------------------------------------------------------- + # Define the exception vectors. rom_vectors: # These are the architecture-defined vectors that # are always present. *************** *** 349,355 **** #ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP # Enable D-Cache hal_dcache_init ! #endif .globl _hal_hardware_init_done _hal_hardware_init_done: --- 416,428 ---- #ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP # Enable D-Cache hal_dcache_init ! #endif ! ! # Start the tick timer, in case timer polling routine hal_delay_us() is called. ! # Initially, no interrupts are generated by the tick timer. Later on, that ! # may change when the kernel is initialized. ! l.movhi r3, hi(0x40000000|CYGNUM_HAL_RTC_PERIOD) ! l.mtspr r0,r3, SPR_TTMR .globl _hal_hardware_init_done _hal_hardware_init_done: *************** *** 369,376 **** hal_vsr_table_init #if defined(CYG_HAL_STARTUP_ROM) ! # Copy exception/interrupt vectors from ROM to address 0x100 ! load32i r4,0x100 load32i r3,rom_vectors load32i r5,rom_vectors_end 1: l.sfeq r3,r5 --- 442,449 ---- hal_vsr_table_init #if defined(CYG_HAL_STARTUP_ROM) ! # Copy exception/interrupt vectors from ROM to address RAM ! load32i r4,RAM_EXCEPTION_VECTOR_BASE_ADDRESS + 0x100 load32i r3,rom_vectors load32i r5,rom_vectors_end 1: l.sfeq r3,r5 *************** *** 394,399 **** --- 467,473 ---- l.j 1b l.addi r4,r4,4 # delay slot 2: + #endif # clear BSS *************** *** 456,463 **** # Call C code # When cyg_hal_exception_handler() returns, it will jump ! # directly to restore_state(), which will resume execution ! # at the location of the exception. l.movhi r9, hi(restore_state) l.j _cyg_hal_exception_handler l.ori r9,r9,lo(restore_state) #Delay slot --- 530,537 ---- # Call C code # When cyg_hal_exception_handler() returns, it will jump ! # directly to restore_state(), which will resume execution ! # at the location of the exception. l.movhi r9, hi(restore_state) l.j _cyg_hal_exception_handler l.ori r9,r9,lo(restore_state) #Delay slot *************** *** 475,481 **** # # After we return here, the saved state is restored and execution is continued. ! FUNC_START(cyg_hal_default_interrupt_vsr) # Stash away pointer to saved regs for later --- 549,560 ---- # # After we return here, the saved state is restored and execution is continued. ! #ifdef CYGIMP_FORCE_INTERRUPT_HANDLING_CODE_IN_RAM ! .section .text.ram,"ax" ! #else ! .section .text,"ax" ! #endif ! FUNC_START(cyg_hal_default_interrupt_vsr) # Stash away pointer to saved regs for later *************** *** 530,573 **** #endif ! # In the event of multiple pending interrupts, determine which ! # one will be serviced first. By software convention, the lowest ! # numbered external interrupt gets priority. ! # ! # The (internal) tick timer interrupt is serviced only if no ! # external interrupts are pending. ! ! # Read the PIC interrupt controller's status register ! l.mfspr r9,r0,SPR_PICSR ! ! # Any pending external interrupts ? ! l.sfnei r9,0 ! l.bf check_for_external_interrupts ! ! # Theoretically, the only way we could get here is if the tick timer ! # interrupt fired, but we check to be sure that's what happened. ! l.sfeqi r4,CYGNUM_HAL_VECTOR_TICK_TIMER ! l.bf 3f ! l.ori r3,r0,CYGNUM_HAL_INTERRUPT_RTC # delay slot - #ifndef CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS - l.jal _hal_spurious_IRQ - l.nop - #endif // CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS - l.j ignore_spurious_interrupt - - # Identify the lowest numbered interrupt bit in the PIC's PSR, - # numbering the MSB as 31 and the LSB as 0 - check_for_external_interrupts: - l.ori r3,r0,0 - 2: l.andi r11,r9,1 # Test low bit - l.sfnei r11,0 - l.bf 3f - l.srli r9,r9,1 # Shift right 1 bit - l.j 2b - l.addi r3,r3,1 # Delay slot - 3: - # At this point, r3 contains the ISR number, from 0-32 # which will be used to index the table of ISRs l.slli r15,r3,2 --- 609,617 ---- #endif ! # Dispatch to ISR based on interrupt controller status ! hal_map_interrupt_to_isr # At this point, r3 contains the ISR number, from 0-32 # which will be used to index the table of ISRs l.slli r15,r3,2 *************** *** 710,715 **** --- 754,760 ---- #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK .extern _cyg_interrupt_call_pending_DSRs + .text FUNC_START(hal_interrupt_stack_call_pending_DSRs) # Switch to interrupt stack l.or r3, sp, sp # Stash entry SP *************** *** 722,729 **** l.sw 8(sp),lr l.jal _cyg_interrupt_call_pending_DSRs ! # Enable interrupts before calling DSRs ! l.mtspr r0, r4, SPR_SR # Delay slot l.lwz r4, 4(sp) l.lwz lr, 8(sp) --- 767,774 ---- l.sw 8(sp),lr l.jal _cyg_interrupt_call_pending_DSRs ! # Enable interrupts before calling DSRs ! l.mtspr r0, r4, SPR_SR # Delay slot l.lwz r4, 4(sp) l.lwz lr, 8(sp) Only in /home/sfurman/ecos/packages/hal/openrisc/: lisa diff -x CVS -c -r ./packages/hal/openrisc/orp/current/cdl/hal_openrisc_orp.cdl /home/sfurman/ecos/packages/hal/openrisc/orp/current/cdl/hal_openrisc_orp.cdl *** ./packages/hal/openrisc/orp/current/cdl/hal_openrisc_orp.cdl 2003-05-07 20:50:05.000000000 -0700 --- /home/sfurman/ecos/packages/hal/openrisc/orp/current/cdl/hal_openrisc_orp.cdl 2003-06-11 14:15:40.000000000 -0700 *************** *** 266,295 **** cdl_option CYGSEM_HAL_USE_ROM_MONITOR { display "Work with a ROM monitor" ! flavor booldata ! legal_values { "Generic" "CygMon" "GDB_stubs" } ! default_value { CYG_HAL_STARTUP == "RAM" ? "CygMon" : 0 } parent CYGPKG_HAL_ROM_MONITOR requires { CYG_HAL_STARTUP == "RAM" } description " ! Support can be enabled for three different varieties of ROM monitor. ! This support changes various eCos semantics such as the encoding ! of diagnostic output, or the overriding of hardware interrupt ! vectors. ! Firstly there is \"Generic\" support which prevents the HAL ! from overriding the hardware vectors that it does not use, to ! instead allow an installed ROM monitor to handle them. This is ! the most basic support which is likely to be common to most ! implementations of ROM monitor. ! \"CygMon\" provides support for the Cygnus ROM Monitor. ! And finally, \"GDB_stubs\" provides support when GDB stubs are ! included in the ROM monitor or boot ROM." } cdl_option CYGSEM_HAL_ROM_MONITOR { display "Behave as a ROM monitor" flavor bool ! default_value 1 parent CYGPKG_HAL_ROM_MONITOR requires { CYG_HAL_STARTUP == "ROM" } description " --- 266,285 ---- cdl_option CYGSEM_HAL_USE_ROM_MONITOR { display "Work with a ROM monitor" ! flavor bool ! default_value { CYG_HAL_STARTUP == "RAM" ? 1 : 0 } parent CYGPKG_HAL_ROM_MONITOR requires { CYG_HAL_STARTUP == "RAM" } description " ! Allow coexistence with ROM monitor (CygMon or GDB stubs) by ! only initializing interrupt vectors on startup, thus leaving ! exception handling to the ROM monitor." } cdl_option CYGSEM_HAL_ROM_MONITOR { display "Behave as a ROM monitor" flavor bool ! default_value 0 parent CYGPKG_HAL_ROM_MONITOR requires { CYG_HAL_STARTUP == "ROM" } description " *************** *** 333,335 **** --- 323,327 ---- puts $cdl_header "#define CYGHWR_HAL_VIRTUAL_VECTOR_TABLE 0xF00" } } + + # EOF hal_openrisc_orp.cdl diff -x CVS -c -r ./packages/hal/openrisc/orp/current/ChangeLog /home/sfurman/ecos/packages/hal/openrisc/orp/current/ChangeLog *** ./packages/hal/openrisc/orp/current/ChangeLog 2003-05-07 20:50:05.000000000 -0700 --- /home/sfurman/ecos/packages/hal/openrisc/orp/current/ChangeLog 2003-06-17 20:21:02.000000000 -0700 *************** *** 1,3 **** --- 1,18 ---- + 2003-05-10 Scott Furman sfurman@rosum.com> + + * include/pkgconf/mlt_openrisc_orp_ram.ldi: Repair memory layout + to accommodate introduction of new sections by jifl. + * include/pkgconf/mlt_openrisc_orp_rom.ldi: Ditto. + + 2003-04-25 Jonathan Larmour jifl@eCosCentric.com> + + * cdl/hal_openrisc_orp.cdl: CYGSEM_HAL_USE_ROM_MONITOR need only be a + bool. + CYGSEM_HAL_ROM_MONITOR should be default off (should be used later...) + * include/pkgconf/mlt_openrisc_orp_ram.ldi: Add sections as per + changes to arch HAL's openrisc.ld. + * include/pkgconf/mlt_openrisc_orp_rom.ldi: Ditto. + 2003-03-06 Scott Furman sfurman@rosum.com> Initial port of eCos to OpenRISC Reference Platform (ORP) diff -x CVS -c -r ./packages/hal/openrisc/orp/current/include/mc.h /home/sfurman/ecos/packages/hal/openrisc/orp/current/include/mc.h *** ./packages/hal/openrisc/orp/current/include/mc.h 2003-05-07 20:50:05.000000000 -0700 --- /home/sfurman/ecos/packages/hal/openrisc/orp/current/include/mc.h 2003-06-11 14:15:40.000000000 -0700 *************** *** 141,143 **** --- 141,145 ---- #define MC_TMS_SYNC_TRDV_WIDTH 8 #endif + + // EOF mc.h diff -x CVS -c -r ./packages/hal/openrisc/orp/current/include/pkgconf/mlt_openrisc_orp_ram.ldi /home/sfurman/ecos/packages/hal/openrisc/orp/current/include/pkgconf/mlt_openrisc_orp_ram.ldi *** ./packages/hal/openrisc/orp/current/include/pkgconf/mlt_openrisc_orp_ram.ldi 2003-05-07 20:50:05.000000000 -0700 --- /home/sfurman/ecos/packages/hal/openrisc/orp/current/include/pkgconf/mlt_openrisc_orp_ram.ldi 2003-06-17 19:55:53.000000000 -0700 *************** *** 11,25 **** SECTIONS { SECTIONS_BEGIN ! SECTION_vectors (ram, 0x00000100, LMA_EQ_VMA) SECTION_text (ram, 0x00008000, LMA_EQ_VMA) SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) ! SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA) ! SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) ! SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); SECTIONS_END } --- 11,40 ---- SECTIONS { SECTIONS_BEGIN ! SECTION_vectors (ram, 0x00000000, LMA_EQ_VMA) SECTION_text (ram, 0x00008000, LMA_EQ_VMA) + + SECTION_data (ram, ALIGN(0x8), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_dynamic (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sdata (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sbss (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) + SECTION_ROMISC (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_init (ram, ALIGN (0x8), LMA_EQ_VMA) SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) ! SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA) ! SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) ! SECTION_ctors (ram, ALIGN (0x8), LMA_EQ_VMA) ! SECTION_dtors (ram, ALIGN (0x8), LMA_EQ_VMA) ! SECTION_devtab (ram, ALIGN (0x8), LMA_EQ_VMA) ! SECTION_lit8 (ram, ALIGN (0x8), LMA_EQ_VMA) ! SECTION_lit4 (ram, ALIGN (0x8), LMA_EQ_VMA) ! CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); SECTIONS_END } diff -x CVS -c -r ./packages/hal/openrisc/orp/current/include/pkgconf/mlt_openrisc_orp_rom.ldi /home/sfurman/ecos/packages/hal/openrisc/orp/current/include/pkgconf/mlt_openrisc_orp_rom.ldi *** ./packages/hal/openrisc/orp/current/include/pkgconf/mlt_openrisc_orp_rom.ldi 2003-05-07 20:50:05.000000000 -0700 --- /home/sfurman/ecos/packages/hal/openrisc/orp/current/include/pkgconf/mlt_openrisc_orp_rom.ldi 2003-06-17 20:00:41.000000000 -0700 *************** *** 11,25 **** SECTIONS { SECTIONS_BEGIN ! SECTION_vectors (rom, 0xF0000100, LMA_EQ_VMA) SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA) SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA) SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) ! SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) ! SECTION_data (ram, 0x1000, FOLLOWING (.gcc_except_table)) ! SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) ! CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); SECTIONS_END } --- 11,46 ---- SECTIONS { SECTIONS_BEGIN ! ! SECTION_vectors (rom, 0xF0000000, LMA_EQ_VMA) ! ! // All eCos code is put in the .text section unless explicitly placed ! // into a section named section .text.ram*. ! SECTION_text_ram (ram, 0x00001000, AT(0xF0001000)) ! SECTION_data (ram, ALIGN(0x8), FOLLOWING(.text.ram)) ! SECTION_got (ram, ALIGN (0x8), FOLLOWING (.data)) ! SECTION_dynamic (ram, ALIGN (0x8), FOLLOWING (.got)) ! SECTION_sdata (ram, ALIGN (0x8), FOLLOWING (.dynamic)) ! SECTION_sbss (ram, ALIGN (0x8), LMA_EQ_VMA) ! SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) ! CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); ! ! . = LOADADDR(.sdata) + SIZEOF(.sdata); ! SECTION_ROMISC (rom, ALIGN (0x8), LMA_EQ_VMA) ! SECTION_RELOCS (rom, ALIGN (0x8), LMA_EQ_VMA) ! SECTION_init (rom, ALIGN (0x8), LMA_EQ_VMA) SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA) SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA) SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) ! SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA) ! SECTION_eh_frame (rom, ALIGN (0x8), LMA_EQ_VMA) ! SECTION_ctors (rom, ALIGN (0x8), LMA_EQ_VMA) ! SECTION_dtors (rom, ALIGN (0x8), LMA_EQ_VMA) ! SECTION_devtab (rom, ALIGN (0x8), LMA_EQ_VMA) ! SECTION_lit8 (rom, ALIGN (0x8), LMA_EQ_VMA) ! SECTION_lit4 (rom, ALIGN (0x8), LMA_EQ_VMA) ! SECTIONS_END } diff -x CVS -c -r ./packages/hal/openrisc/orp/current/include/platform.inc /home/sfurman/ecos/packages/hal/openrisc/orp/current/include/platform.inc *** ./packages/hal/openrisc/orp/current/include/platform.inc 2003-05-07 20:50:05.000000000 -0700 --- /home/sfurman/ecos/packages/hal/openrisc/orp/current/include/platform.inc 2003-06-11 14:15:40.000000000 -0700 *************** *** 112,114 **** --- 112,118 ---- .endm #endif /* ifndef _PLATFORM_INC_ */ + + #undef CYGIMP_FORCE_INTERRUPT_HANDLING_CODE_IN_RAM + + // EOF platform.inc diff -x CVS -c -r ./packages/hal/openrisc/orp/current/src/hal_diag.c /home/sfurman/ecos/packages/hal/openrisc/orp/current/src/hal_diag.c *** ./packages/hal/openrisc/orp/current/src/hal_diag.c 2003-05-07 20:50:06.000000000 -0700 --- /home/sfurman/ecos/packages/hal/openrisc/orp/current/src/hal_diag.c 2003-06-11 14:15:40.000000000 -0700 *************** *** 590,594 **** } //----------------------------------------------------------------------------- ! // end of ser16c550c.c ! --- 590,593 ---- } //----------------------------------------------------------------------------- ! // end of hal_diag.c

* Scott Furman (sfurman@rosum.com) wrote:

the ecos in CVS is not exacly v2.0 release, but a cvs snapshot
just before 2.0 release. my idea was to wait till i have ecos working then
import ecos-2.0 with latest openrisc patches. so i suggest we just
forget (ie backup it somwhere then remove it) the current version in
opencores cvs and then import a real ecos-2.0 with the latest patches.

i've been running ecos tests compiled gcc-3.1 +
your gcc patch for a few hours now and results are looking good. the
'unknown status' means there wa not 'PASS' or 'FAIL' string in the output.
in cases i checked it was a problem of stopping simulations
to soon. (10 000 000 instructions)... quite a few tests that didn't pass
with OC+UC gcc-3.2.3 pass now...

running './abs' ecos test: passed
running './cos' ecos test: unknown status
running './div' ecos test: passed
running './exp' ecos test: unknown status
running './log' ecos test: unknown status
running './pow' ecos test: unknown status
running './sin' ecos test: unknown status
running './tan' ecos test: unknown status
running './acos' ecos test: passed
running './asin' ecos test: passed
running './atan' ecos test: unknown status
running './atoi' ecos test: passed
running './atol' ecos test: passed
running './ceil' ecos test: passed
running './cosh' ecos test: unknown status
running './fabs' ecos test: passed
running './fmod' ecos test: passed
running './kill' ecos test: unknown status
running './labs' ecos test: passed
running './ldiv' ecos test: passed
running './modf' ecos test: passed
running './sinh' ecos test: unknown status
running './tanh' ecos test: unknown status
running './sqrt' ecos test: passed
running './time' ecos test: passed
running './kcache1' ecos test: unknown status
running './kcache2' ecos test: passed
running './context' ecos test: passed
running './kclock0' ecos test: passed
running './kclock1' ecos test: unknown status
running './clockcnv' ecos test: unknown status
running './realloc' ecos test: passed
running './release' ecos test: passed
running './wallclock' ecos test: unknown status
running './wallclock2' ecos test: passed
running './basic' ecos test: passed
running './atan2' ecos test: unknown status
running './cache' ecos test: unknown status
running './clock' ecos test: unknown status
running './ctime' ecos test: passed
running './ctype' ecos test: passed
running './flag0' ecos test: passed
running './flag1' ecos test: unknown status
running './floor' ecos test: passed
running './frexp' ecos test: passed
running './intr0' ecos test: passed
running './klock' ecos test: passed
running './ldexp' ecos test: passed
running './ksem0' ecos test: passed
running './ksem1' ecos test: passed
running './mbox1' ecos test: passed
running './log10' ecos test: unknown status
running './rand1' ecos test: passed
running './rand2' ecos test: passed
running './rand3' ecos test: unknown status
running './rand4' ecos test: passed
running './qsort' ecos test: passed
running './srand' ecos test: passed
running './sync2' ecos test: passed
running './sync3' ecos test: passed
running './kmutex0' ecos test: passed
running './kmutex1' ecos test: passed
running './kmutex3' ecos test: unknown status
running './kmutex4' ecos test: unknown status
running './tm_basic' ecos test: unknown status
running './ksched1' ecos test: passed
running './timeslice' ecos test: unknown status
running './signal1' ecos test: FAILED
running './malloc1' ecos test: passed
running './malloc2' ecos test: unknown status
running './malloc3' ecos test: passed
running './malloc4' ecos test: unknown status
running './sprintf1' ecos test: passed
running './sprintf2' ecos test: passed
running './memcmp1' ecos test: passed
running './memcmp2' ecos test: passed
running './memcpy1' ecos test: passed
running './memcpy2' ecos test: passed
running './memfix1' ecos test: unknown status
running './memfix2' ecos test: passed
running './memvar1' ecos test: passed
running './memvar2' ecos test: passed
running './cnt_sem0' ecos test: passed
running './cnt_sem1' ecos test: passed
running './setlocale' ecos test: passed
running './thread0' ecos test: passed
running './thread1' ecos test: passed
running './thread2' ecos test: passed
running './atexit' ecos test: passed
running './except1' ecos test: passed
running './strcat1' ecos test: passed
running './strcat2' ecos test: passed
running './strcmp1' ecos test: passed
running './strcmp2' ecos test: passed
running './strcpy1' ecos test: passed
running './strcpy2' ecos test: passed
running './strcspn' ecos test: passed
running './strpbrk' ecos test: passed
running './strrchr' ecos test: passed
running './strtoul' ecos test: passed
running './clock0' ecos test: passed
running './clock1' ecos test: unknown status
running './i18nmb' ecos test: passed
running './dhrystone' ecos test: unknown status
running './getenv' ecos test: passed
running './fptest' ecos test: unknown status
running './gmtime' ecos test: passed
running './mqueue1' ecos test: passed

I'm all for it - in fact I was going to suggest just that :)

Heiko