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JTAG unstable
by Unknown on Jan 28, 2004 |
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We implemented OR1200 in FPGA board (AVNET XC2V40000)
One problem is JTAG often failed. By linking the state machine signal outside, we found sometime the statemachine run into dead state (ALL state signal is 0). We add extra logic to prevent this situation.( When all state went into dead, recover it to reset/idle). It works well now. I don't know what's the possible reason to cause it. JTAG_CLK routine problem? Shawn |
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JTAG unstable
by Unknown on Jan 29, 2004 |
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Hi, Shawn.
That happened when the TAP was not reset OK. When TRST is used it shouldn't happen. Now the TAP was rewritten and it is reset after 5 TCK cycles while TMS is at 1. Probably you had glitches on TCK that caused all these problems. Regards, Igor
-----Original Message-----
From: openrisc-bounces@opencores.org [mailto:openrisc-
bounces@opencores.org] On Behalf Of shawn_chen_eda@yahoo.com
Sent: Wednesday, January 28, 2004 11:55 PM
To: openrisc@opencores.org
Subject: [openrisc] JTAG unstable
We implemented OR1200 in FPGA board (AVNET XC2V40000)
One problem is JTAG often failed. By linking the state machine
signal outside, we found sometime the statemachine run into
dead state (ALL state signal is 0). We add extra logic to prevent
this situation.( When all state went into dead, recover it to
reset/idle).
It works well now. I don't know what's the possible reason
to cause it. JTAG_CLK routine problem?
Shawn
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