I'm currently completing the or1ksim debug unit implementation with the
DVR/DCR examination. The execution unit calls the debug units for
Instruction Fetch, Load Address, Store Address, Load Data and Store
Data. The CPU knows two more compare modes: Load/Store Address and
Load/Store Data. How do these work? Is Load/Store Address a check if
there is either a load or a store to the address?

And another thing. The Load/Store Address compare type is already in the header files. The Load/Store Data compare type is mentioned nowhere in or1ksim. Should this type be implemented too? _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc